초록 ▼

In a memory protection system for a computer, memory protection information provided for each of the memory areas of a memory and memory protection information provided for each of the programs executed by a processor are collated to determine allowance/inhibition of access to the memory. By detecti

In a memory protection system for a computer, memory protection information provided for each of the memory areas of a memory and memory protection information provided for each of the programs executed by a processor are collated to determine allowance/inhibition of access to the memory. By detecting that an instruction to be executed is an instruction having a particular operation and that an address of the memory to be accessed by the instruction is a particular address, the memory protection information for the program executed by the processor is alterd to allow the memory access. The alteration of memory protection information is carried out with no intervention of a control program.

대표청구항 ▼

A memory protection system for use in a data processing system including a main memory having a plurality of memory areas accessed by respective memory addresses and a program implemented processor for accessing said main memory by application of selected addresses thereto, comprising: first storage

A memory protection system for use in a data processing system including a main memory having a plurality of memory areas accessed by respective memory addresses and a program implemented processor for accessing said main memory by application of selected addresses thereto, comprising: first storage means for storing therein first predetermined protection information for each of the respective memory areas of said main memory; second storage means for storing therein second predetermined protection information for a selected program to be performed by said processor; first detecting means for detecting that an instruction to be executed by said processor is a predetermined instruction; second detecting means for detecting that an address for access to said main memory specified by said predetermined instruction is a predetermined address; determining means connected to said first and second storage means for collating the first protection information stored in said first storage means corresponding to one of the memory areas accessible by an address stored at said predetermined address in said main memory with the second protection information stored in said second storage means, thereby to determine whether the memory access is to be allowed or inhibited; and altering means responsive to outputs of said first and second detecting means for altering the second protection information stored in said second storage means, when said first detecting means detects that an instruction to be executed is a predetermined instruction and said second detecting means detects that the address specified by the predetermined instruction is a predetermined address.