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Cache/disk subsystem with dual aging of cache entries 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/00
출원번호 US-0207059 (1980-11-14)
발명자 / 주소
  • Sawyer Daniel D. (Roseville MN) Thompson Marvin J. (Anoka MN)
출원인 / 주소
  • Sperry Corporation (New York NY 02)
인용정보 피인용 횟수 : 27  인용 특허 : 7

초록

When a processor issues a read or write command to read one or more words from a disk, a cache store is checked to see if a copy of the segment(s) containing the word(s) are present therein. If a copy of the segment is not present in the cache store then it is moved from disk to the cache store and

대표청구항

In a data processing system including a host processor for issuing addressing signals specifying data to be accessed, a mass memory, a cache store for storing segments, and a segment descriptor table for storing segment descriptors, there being a segment descriptor associated with each data segment

이 특허에 인용된 특허 (7)

  1. Ryan Charles P. (Phoenix AZ), Buffer store including control apparatus which facilitates the concurrent processing of a plurality of commands.
  2. Porter Marion G. (Phoenix AZ) Norman ; Jr. Robert W. (Glendale AZ) Flynn Richard T. (Peoria AZ), Cache unit bypass apparatus.
  3. Hattori Akira (Yokohama JPX) Tsuchimoto Takamitsu (Machida JPX), Data processing system having an intermediate buffer memory.
  4. Coombes Daniel J. (Glen Ellyn IL) Messina Benedicto U. (Poughkeepsie NY), Fault tolerant least recently used algorithm logic.
  5. Ghyczy Miklos (Cologne DEX) Erds Adorjan (Cologne DEX) Heidemann Gnter (Geilenkirchen-Tripsrath DEX) Ritzmann Gtz (Cologne DEX), Inflammation-preventing pharmaceutical composition of oral administration.
  6. DeKarske Clarence W. (St. Paul Park MN), Paired least recently used block replacement system.
  7. Joyce Thomas F. (Burlington MA) Holtey Thomas O. (Newton Lower Falls MA), Private cache-to-CPU interface in a bus oriented data processing system.

이 특허를 인용한 특허 (27)

  1. Alvarez ; II Manuel J. (Binghamton NY) Jackson ; Jr. Earl W. (Apalachin NY), Accelerated data transfer mechanism using modified clock cycle.
  2. Pomerene James H. (Chappaqua NY) Puzak Thomas R. (Cary NC) Rechtschaffen Rudolph N. (Scarsdale NY) So Kimming (Pleasantville NY), Apparatus and method for prefetching subblocks from a low speed memory to a high speed memory of a memory hierarchy depe.
  3. Matsunami Naoto,JPX ; Yoshida Minoru,JPX ; Miyazawa Shoichi,JPX ; Oeda Takashi,JPX ; Honda Kiyoshi,JPX ; Ohno Shuji,JPX, Array disk controller for grouping host commands into a single virtual host command.
  4. Macon ; Jr. James F. (Boynton Beach FL) Ong Shauchi (San Jose CA) Shih Feng-Hsien W. (Hsien-Chu TWX), Asynchronous read-ahead disk caching using multiple disk I/O processes adn dynamically variable prefetch length.
  5. Cohn, Oded; Dekel, Eliezer; Rodeh, Michael, Cache control system.
  6. Nomura, Kumiko; Abe, Keiko; Fujita, Shinobu, Cache system and processing apparatus.
  7. Schafer Bruce W. ; Teeters Jeffrey W. ; Chweh Mark C. ; Lee David A. ; O'Connell Daniel P. ; Ramanathan Gowri, Caching apparatus and method for enhancing retrieval of data from an optical storage device.
  8. Easton Malcolm C. (San Jose CA) Howard John H. (Pittsburgh PA), DASD cache block staging.
  9. Hronik,Stanley A., Double data rate synchronous SRAM with 100% bus utilization.
  10. Mick, John R., Fully synchronous pipelined RAM.
  11. Mick, John R., Fully synchronous pipelined RAM.
  12. Lewis David O. (Rochester MN) McMahon Lynn A. (Rochester MN) Schardt Terry L. (Rochester MN), Look-aside buffer LRU marker controller.
  13. McNutt, Bruce, Method and apparatus for providing efficient management of least recently used (LRU) algorithm insertion points corresponding to defined times-in-cache.
  14. Beardsley Brent Cameron ; Benhase Michael Thomas ; Martin Douglas A. ; Morton Robert Louis ; Reid Mark A., Method and system for managing data in cache.
  15. Beardsley Brent Cameron ; Benhase Michael Thomas ; Martin Douglas A. ; Morton Robert Louis ; Reid Mark A., Method and system for managing data in cache using multiple data structures.
  16. Clark Debs Jeffries ; Piyush Chunilal Patel ; Gail Irene Woodland, Method and system for performing variable aging to optimize a memory resource.
  17. Brent Cameron Beardsley ; Michael Thomas Benhase ; Joseph Smith Hyde ; Thomas Charles Jarvis ; Douglas A. Martin ; Robert Louis Morton, Method and system for staging data into cache.
  18. Lautzenheiser Marvin (Springfield VA), Method for operating a cache memory system using a recycled register for identifying a reuse status of a corresponding c.
  19. Sciupac Luis H. (Santa Clara CA), Method of reading and writing files on nonerasable storage media.
  20. Brenza James G. (Putnam Valley NY), Partitioned cache memory with partition look-aside table (PLAT) for early partition assignment identification.
  21. Iskiyan James L. (Tucson AZ) Legvold Vernon J. (Tucson AZ) Leung Peter L. H. (Tucson AZ) Martin Guy E. (Tucson AZ), Peripheral subsystem having read/write cache with record access.
  22. Legvold Vernon J. (Tucson AZ) Wellons Stephen O. (Tucson AZ), Peripheral subsystem initialization method and apparatus.
  23. Mick, John R.; Baumann, Mark W., Separate byte control on fully synchronous pipelined SRAM.
  24. Anemojanis Eugene, System for identifying memory segment bounded by previously accessed memory locations within data block and transferring.
  25. Brenner Larry B. (Stone Ridge NY) VanLeer Paul W. (Highland NY), System for periodically reallocating page frames in memory based upon non-usage within a time period or after being allo.
  26. Idleman Thomas E. (Santa Clara CA) Stamness Jesse I. (Sunnyvale CA), Variable rate improvement of disc cache subsystem.
  27. Zhu, Ming Benjamin; Patterson, R. Hugo; Bricker, Allan J.; Lee, Edward K., Write latency efficient storage system.
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