$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Lift-off process for fabricating self-aligned contacts 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B05D-005/12
출원번호 US-0404109 (1982-08-02)
발명자 / 주소
  • Milgram Alvin (Sunnyvale CA)
출원인 / 주소
  • Fairchild Camera & Instrument Corporation (Mountain View CA 02)
인용정보 피인용 횟수 : 49  인용 특허 : 5

초록

A process is provided for fabricating self-aligned contacts to the surface of an integrated circuit. The process includes the steps of depositing a layer of silicon dioxide 12 on the surface of a semiconductor structure 10; depositing a layer of polyimide 15 on the surface of the silicon dioxide 12;

대표청구항

A lift-off process for fabricating self-aligned regions of first and second material on the surface of semiconductor structure comprising; depositing a layer of first material on the surface of the semiconductor; depositing a layer of a polyamide on the layer of first material; depositing at least o

이 특허에 인용된 특허 (5)

  1. Corbin ; Vivian Ruth ; Hitchner ; James Edward ; Patnaik ; Bisweswar ; Ting ; Chung-Yu, Forming self-aligned via holes in thin film interconnection systems.
  2. Saiki Atsushi (Musahimurayama JPX) Okubo Toshio (Tokyo JPX) Harada Seiki (Hachioji JPX), Method for fabricating semiconductor device and etchant for polymer resin.
  3. Moritz, Holger, Method of making conductive paths through a lamina in a semiconductor device.
  4. Zielinski Laura B. (Plantsville CT), Process for forming passivated metal interconnection system with a planar surface.
  5. Adams Arthur C. (Berkeley Heights NJ) Alexander ; Jr. Frank B. (Totowa NJ) Levinstein Hyman J. (Berkeley Heights NJ) Thibault Louis R. (Piscataway NJ), Reducing charging effects in charged-particle-beam lithography.

이 특허를 인용한 특허 (49)

  1. Sreenivasan, Sidlgata V; Watts, Michael P. C.; Choi, Byung J.; Voisin, Ronald D., Alignment methods for imprint lithography.
  2. Xu,Frank Y.; Miller,Michael N.; Watts,Michael P. C., Composition for an etching mask comprising a silicon-containing material.
  3. Sreenivasan,Sidlgata V., Eliminating printability of sub-resolution defects in imprint lithography.
  4. Choi, Byung J.; Sreenivasan, Sidlgata V., Flexure based macro motion translation stage.
  5. Choi, Byung Jin; Meissl, Mario J.; Sreenivasan, Sidlagata V.; Watts, Michael P. C., Formation of discontinuous films during an imprint lithography process.
  6. Choi,Byung Jin; Meissl,Mario J.; Sreenivasan,Sidlagata V.; Watts,Michael P. C., Formation of discontinuous films during an imprint lithography process.
  7. Choi, Byung Jin; Sreenivasan, Sidlgata V.; Johnson, Stephen C., High precision orientation alignment and gap control stages for imprint lithography processes.
  8. Sreenivasan, Sidlgata V.; Choi, Byung J.; Colburn, Matthew; Bailey, Todd, High-resolution overlay alignment methods for imprint lithography.
  9. Sreenivasan,Sidlgata V.; Schumaker,Philip D., Imprint lithography template having opaque alignment marks.
  10. Sreenivasan, Sidlgata V.; Choi, Byung-Jin, Imprinting of partial fields at the edge of the wafer.
  11. Ahn, Byung Chul; Lim, Joo Soo; Park, Byung Ho, Liquid crystal display device and fabricating method thereof.
  12. Ahn,Byung Chul; Lim,Joo Soo; Park,Byung Ho, Liquid crystal display device and fabricating method thereof.
  13. Xu, Frank Y.; Watts, Michael P. C.; Stacey, Nicholas A., Materials for imprint lithography.
  14. Choi, Byung-Jin; Sreenivasan, Sidlgata V., Method and system for double-sided patterning of substrates.
  15. Watts,Michael P. C.; Sreenivasan,Sidlgata V., Method for fabricating bulbous-shaped vias.
  16. Willson, Carlton Grant; Sreenivasan, Sidlgata V.; Bonnecaze, Roger T., Method for fabricating nanoscale patterns in light curable compositions using an electric field.
  17. Ye Yan ; Zhao Allen ; Hsieh Peter Chang-Lin ; Ma Diana Xiaobing, Method for high temperature etching of patterned layers using an organic mask stack.
  18. Mayr Kurt (Wangle ATX) Staffler Reinhard (Ehenbichl ATX) Tippelt Werner (Linz ATX) Scharizer Walter (Gallneukirchen ATX), Method for making a composite substrate for electronic semiconductor parts.
  19. Kobayashi Junichiro (Kanagawa JPX) Hiramatsu Shigeru (Kanagawa JPX) Takakuwa Hidemi (Kanagawa JPX), Method for manufacture of semiconductor device.
  20. Huebner Holger (Baldham DEX), Method for producing a resist structure on a semiconductor.
  21. Choi, Byung-Jin; Sreenivasan, Sidlgata V.; Willson, Carlton Grant; Colburn, Mattherw E.; Bailey, Todd C.; Ekerdt, John G., Method of automatic fluid dispensing for imprint lithography processes.
  22. Sreenivasan, Sidlgata V.; McMackin, Ian M.; Melliar-Smith, Christopher Mark; Choi, Byung-Jin, Method of concurrently patterning a substrate having a plurality of fields and a plurality of alignment marks.
  23. Yan Ye ; Pavel Ionov ; Allen Zhao ; Peter Hsieh ; Diana Ma ; Chun Yan ; Jie Yuan, Method of etching dielectric layers using a removable hardmask.
  24. Ye Yan ; Ionov Pavel ; Zhao Allen ; Hsieh Peter Chang-Lin ; Ma Diana Xiaobing ; Yan Chun ; Yuan Jie, Method of etching patterned layers useful as masking during subsequent etching or for damascene structures.
  25. Baars, Peter; Wei, Andy; Geiss, Erik; Mazur, Martin, Method of forming self-aligned contacts for a semiconductor device.
  26. Ye Yan ; Ionov Pavel ; Zhao Allen ; Hsieh Peter Chang-Lin ; Ma Diana Xiaobing ; Yan Chun ; Yuan Jie, Method of pattern etching a low K dielectric layer.
  27. Akira Shuhara (Amagasaki JPX) Kenichiro Yamanishi (Amagasaki JPX) Yoshibumi Minowa (Amagasaki JPX), Method of producing silicon dioxide films.
  28. Rubin, Daniel I., Method of reducing pattern distortions during imprint lithography processes.
  29. Sreenivasan, Sidlgata V.; Watts, Michael P. C., Method to arrange features on a substrate to replicate features having minimal dimensional variability.
  30. Choi,Byung Jin; Xu,Frank Y.; Stacey,Nicholas A.; Truskett,Van Xuan Hong; Watts,Michael P. C., Method to reduce adhesion between a conformable region and a pattern of a mold.
  31. Truskett,Van N.; Mackay,Christopher J.; Choi,B. Jin, Method to reduce adhesion between a polymerizable layer and a substrate employing a fluorine-containing layer.
  32. Xu,Frank Y.; Stacey,Nicholas E.; Watts,Michael P. C.; Thompson,Ecron D., Methods for fabricating patterned features utilizing imprint lithography.
  33. Choi, Byung J.; Colburn, Matthew; Sreenivasan, S. V.; Willson, C. Grant; Bailey, Todd; Ekerdt, John, Methods for high-precision gap and orientation sensing between a transparent template and substrate for imprint lithography.
  34. Xie, Ruilong; Cai, Xiuyu, Methods of forming semiconductor device with self-aligned contact elements and the resulting device.
  35. Xie, Ruilong; Cai, Xiuyu, Methods of forming semiconductor device with self-aligned contact elements and the resulting device.
  36. Cai, Xiuyu; Xie, Ruilong; Iacoponi, John A., Methods of forming semiconductor device with self-aligned contact elements and the resulting devices.
  37. Cai, Xiuyu; Xie, Ruilong; Iacoponi, John A., Methods of forming semiconductor device with self-aligned contact elements and the resulting devices.
  38. Sreenivasan, Sidlgata V.; Schumaker, Philip D., Patterning a plurality of fields on a substrate to compensate for differing evaporation times.
  39. Choi, Byung-Jin; Sreenivasan, Sidlgata V., Patterning substrates employing multiple chucks.
  40. Cohen, Guy M.; Engelmann, Sebastian U.; Holmes, Steve; Patel, Jyotica V., Reactive ion etching assisted lift-off processes for fabricating thick metallization patterns with tight pitch.
  41. Schmid, Gerard M.; Stacey, Nicholas A; Resnick, Douglas J.; Voisin, Ronald D.; Myron, Lawrence J., Self-aligned process for fabricating imprint templates containing variously etched features.
  42. Matsuo Seitaro (Hachioji JPX) Muramoto Susumu (Hachioji JPX) Ehara Kohei (Kodaira JPX) Itsumi Manabu (Hoya JPX), Semiconductor device and manufacturing process thereof.
  43. Sreenivasan, Sidlgata V.; Choi, Byung J.; Schumaker, Norman E.; Voisin, Ronald D.; Watts, Michael P. C.; Meissl, Mario J., Step and repeat imprint lithography processes.
  44. Sreenivasan,Sidlgata V.; Choi,Byung J.; Schumaker,Norman E.; Voisin,Ronald D.; Watts,Michael P. C.; Meissl,Mario J., Step and repeat imprint lithography processes.
  45. Choi,Byung J.; Sreenivasan,Sidlgata V., System for determining characteristics of substrates employing fluid geometries.
  46. GanapathiSubramanian, Mahadevan; Choi, Byung-Jin; Miller, Michael N.; Stacey, Nicholas A., Technique for separating a mold from solidified imprinting material.
  47. Bailey, Todd; Choi, Byung J.; Colburn, Matthew; Sreenivasan, S. V.; Willson, C. Grant; Ekerdt, John, Template for room temperature, low pressure micro-and nano-imprint lithography.
  48. Selinidis, Kosta S.; Choi, Byung-Jin; Schmid, Gerard M.; Thompson, Ecron D.; McMackin, Ian Matthew, Template having alignment marks formed of contrast material.
  49. Sreenivasan, Sidlgata V.; Schumaker, Philip D.; McMackin, Ian M., Tessellated patterns in imprint lithography.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로