초록 ▼

Address generating apparatus which uses narrow data paths for generating a wide logical address and which also provides for programs to access very large shared data structures outside their normally available addressing range and over an extended range of addresses. Selective indexed addressing is

Address generating apparatus which uses narrow data paths for generating a wide logical address and which also provides for programs to access very large shared data structures outside their normally available addressing range and over an extended range of addresses. Selective indexed addressing is employed for providing index data which is also used for deriving variable dimension override data. During address generation, selected index data is added to a displacement provided by an instruction for deriving a dimension override value as well as an offset. The derived dimension override value is used to selectively access an address locating entry in a table of entries corresponding to the applicable program. The resulting accessed address locating entry is in turn used to determine the particular portion of memory against which the offset is to be applied.

대표청구항 ▼

In a data processing system having a memory and an address translator, improved apparatus for generating a logical address for use by said translator in accessing said memory, said apparatus comprising: means for storing data indicative of a logical address, said data including index selection data

In a data processing system having a memory and an address translator, improved apparatus for generating a logical address for use by said translator in accessing said memory, said apparatus comprising: means for storing data indicative of a logical address, said data including index selection data and displacement data; a plurality of index registers each including index data; means responsive to said index selection data for selecting one of said index registers; an extended address register; means including an adder for adding the index data in a selected index register to said displacement data and for storing the sum in said extended address register; a logical address register having first and second portions; means for storing a predetermined number of the least significant digits of the sum in said extended address register in said first portion of said logical address register; table storing means for storing a plurality of tables each containing a plurality of address locating entries for a corresponding one of a plurality of programs performable by said system; selection means responsive to a program identification signal provided by said system and to a predetermined number of the most significant digits of the sum in said extended address register for accessing a corresponding one of the address locating entries in a selected one of said tables and for storing this accessed entry in said second portion of said logical address register; and means for applying the contents of the first and second portions of said logical address register to said address translator.