초록 ▼

A cache is accessed based upon addresses to a backing store having a larger address space than the cache. The backing store consists of plurality of devices exhibiting delay access boundaries. The cache accessing is based upon a hashing method and system derived from the arrangement of the backing s

A cache is accessed based upon addresses to a backing store having a larger address space than the cache. The backing store consists of plurality of devices exhibiting delay access boundaries. The cache accessing is based upon a hashing method and system derived from the arrangement of the backing store and in an ordered manner for accommodating the delay access boundaries and enable rapidly adjusting the hash parameters in accordance with changes and backing store capability in other hardware changes.

대표청구항 ▼

The method of indirectly addressing a buffer memory having a first plurality of addressable buffer segments and being coupled to a backing memory having a second plurality of addressable memory segments distributed among a given plurality of addressable data storage devices, said second plurality of

The method of indirectly addressing a buffer memory having a first plurality of addressable buffer segments and being coupled to a backing memory having a second plurality of addressable memory segments distributed among a given plurality of addressable data storage devices, said second plurality of addressable memory segments being more than either said first plurality of buffer segments or said given plurality of data storage devices; the method employing the numerical relationships of the second plurality of memory segments to the given plurality of data storage devices, comprising the machine-implemented steps of: establishing a directory with entries for respectively identifying said buffer segments for individually addressing same, and each entry having link elements for linking entries into address classes to form a linked list in each of said address classes; establishing and maintaining a scatter index table (SIT) for containing signals stored in a given number of addressable fields for pointing to said linked entries of one of said address classes, one signal pointer for each of said address classes in each of said addressable fields; sequentially addressing said SIT addressable fields for accessing said signal pointers to address said linked entries of said address classes in said directory; after accessing each of said signal pointers, addressing said linked entries in said directory using said accessed signal pointers, respectively, for accessing said buffer segments which are to store data corresponding to data stored in respective ones of said memory segments in respective ones of said addressable data storage devices identified in said SIT fields; and each of said linked entries having addresses of said addressable memory segments separated by a number of addresses equal to the quotient of said second plurality divided by said given plurality such that said memory segments of said respective data storage devices bearing the same address within the respective data storage devices are assigned to different ones of said address classes.