초록 ▼

The present invention is an electronic controller that is partially a virtual machine. The virtual machine portion of the controller comprises an Operating System including two major levels－namely, an Instruction Module level and a Primitive level. Directives corresponding to macros in a physical ma

The present invention is an electronic controller that is partially a virtual machine. The virtual machine portion of the controller comprises an Operating System including two major levels－namely, an Instruction Module level and a Primitive level. Directives corresponding to macros in a physical machine (microprocessor) architecture are the top level of the control. The Directives shield the Operating System structure from changes in the compiler, allow for changes in the Operating System internal structure and abstract out from the compiler unnecessary operating system details. Instruction Modules and Primitives make up the Operating System. Instruction Modules are the middle level and correspond to assembly language instructions in a physical machine. They are the smallest executable, nonpreemptive unit in the virtual machine. Preemption is similar to a physical machine interrupt capability except that a physical machine allows basically two concurrent processes or tasks (foreground or background) whereas the virtual machine allows an almost unlimited number of tasks executing in one or more physical processors.

대표청구항 ▼

In a machine having a plurality of operating components, a control for coordinating the operation of the operating components, the control including at least one processor and a virtual machine portion, the control responding to high level and processor level instructions, said virtual machine porti

In a machine having a plurality of operating components, a control for coordinating the operation of the operating components, the control including at least one processor and a virtual machine portion, the control responding to high level and processor level instructions, said virtual machine portion providing a link between said high level instructions and said processor level instructions.