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Centralized hardware control of multisystem access to shared and non-shared subsystems 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/16
출원번호 US-0395936 (1982-07-07)
발명자 / 주소
  • Quernemoen John M. (New Brighton MN) Voltz Timothy R. (St. Paul MN) Campbell Richard P. (Blaine MN) Kriscunas Joseph G. (Blaine MN)
출원인 / 주소
  • Sperry Corporation (New York NY 02)
인용정보 피인용 횟수 : 37  인용 특허 : 1

초록

A centralized control unit for use in a multisystem data processing configuration to provide dynamic access to shared and non-shared peripheral subsystems is disclosed. This unit, known herein as a subsystem access unit (SAU) is able to remotely control one or more system\s accessibility to peripher

대표청구항

A central controlling unit, for use with a plurality of data processing systems, none, some, or all of which are capable of being partitioned into a further plurality of separate entities, having the characteristics of a complete data processing system and a plurality of subsystem interface connecti

이 특허에 인용된 특허 (1)

  1. Patterson Garvin Wesley (Glendale AZ) Shelly William A. (Phoenix AZ) Monahan Earnest M. (Phoenix AZ), Steering code generating apparatus for use in an input/output processing system.

이 특허를 인용한 특허 (37)

  1. Zelley Richard C. (North Chelmsford MA) Kenna ; Jr. Mark J. (Merrimack NH) Martland ; deceased Wallace A. (late of Amherst NH by Sheila M. Martland ; administratrix), Apparatus and method of loading a control store memory of a central subsystem.
  2. Griessbach, Gunter; Ramm, Enrico; Weissbach, Bernhard, Bus master switching unit.
  3. Quernemoen, John M.; Hazzard, Mark G., Combination of mass storage sizer, comparator, OLTP user defined workload sizer, and design.
  4. Berger Michael F. (Fort Worth TX), Computer revision port.
  5. Elko, David A.; Goss, Steven N.; Jordan, Michael J.; Kurdt, Georgette L.; Nick, Jeffrey M.; Pushong, Kelly B.; Surman, David H., Controlling the state of duplexing of coupling facility structures.
  6. Elko, David A.; Goss, Steven N.; Jordan, Michael J.; Kurdt, Georgette L.; Nick, Jeffrey M.; Pushong, Kelly B.; Surman, David H., Controlling the state of duplexing of coupling facility structures.
  7. Elko, David A.; Goss, Steven N.; Jordan, Michael J.; Kurdt, Georgette L.; Nick, Jeffrey M.; Pushong, Kelly B.; Surman, David H., Controlling the state of duplexing of coupling facility structures.
  8. Elko, David A.; Goss, Steven N.; Jordan, Michael J.; Kurdt, Georgette L.; Nick, Jeffrey M.; Pushong, Kelly B.; Surman, David H., Controlling the state of duplexing of coupling facility structures.
  9. Jakobs Thomas ; Jung Wayne D. ; Karlin Richard A. ; Reiffel Leonard ; Tam Raphael K. ; Tutt Timothy T. ; Dunk Michael F., Image processing apparatus having common and personal memory and capable of viewing and editing an image commonly with a.
  10. Abbondanzio, Antonio; Ashok, Shamsundar; Jones, NicoleLyne; Jurgensen, Dennis Duane; Kocheisen, Rolf; Koyfman, Yan Schloem; Pitz, Sherry Michelle; Richman, Peter Andrew; Snyder, Devon Daniel; Vanca, William John; Warren, Philip Kincheloe; Warren, Robert Edward, Load balancing management of newly discovered data processing systems using peer control points.
  11. Boudreau Daniel A. (Billerica MA) Sandini James M. (Berlin MA) Salas Edward R. (Billerica MA), Lockout operation among asynchronous accessers of a shared computer system resource.
  12. Andre, Rodney C.; McCrary, Rex E., Mechanism for granting controlled access to a shared resource.
  13. Andre, Rodney C.; McCrary, Rex E., Mechanism for granting controlled access to a shared resource.
  14. Deshpande, Sanjay Raghunath, Method and apparatus for achieving correct order among bus memory transactions in a physically distributed SMP system.
  15. Kruse, Robert Earl, Method and apparatus for avoiding data bus grant starvation in a non-fair, prioritized arbiter for a split bus system with independent address and data bus grants.
  16. Kruse, Robert Earl, Method and apparatus for increased performance of a parked data bus in the non-parked direction.
  17. Kruse, Robert Earl, Method and apparatus for synchronizing multiple bus arbiters on separate chips to give simultaneous grants for the purpose of breaking livelocks.
  18. Deshpande, Sanjay Raghunath; Kruse, Robert Earl, Method and apparatus for transaction pacing to reduce destructive interference between successive transactions in a distributed symmetric multiprocessor system.
  19. Alvarez, II, Manuel Joseph; Deshpande, Sanjay Raghunath; Klapproth, Kenneth Douglas; Mui, David, Method and apparatus for transaction tag assignment and maintenance in a distributed symmetric multiprocessor system.
  20. Deshpande, Sanjay Raghunath; Kruse, Robert Earl, Method and apparatus to distribute interrupts to multiple interrupt handlers in a distributed symmetric multiprocessor system.
  21. Kruse, Robert Earl; Milling, Philip Erna, Method and apparatus to eliminate failed snoops of transactions caused by bus timing conflicts in a distributed symmetric multiprocessor system.
  22. Manuel Alvarez ; Sanjay Raghunath Deshpande ; Peter Dau Geiger ; Jeffrey Holland Gruger, Method and apparatus using a distributed system structure to support bus-based cache-coherence protocols for symmetric multiprocessors.
  23. Alvarez, II, Manuel Joseph; Davidson, Joel Roger; Deshpande, Sanjay Raghunath; Geiger, Peter Dau; Powell, Lawrence Joseph; Reddy, Praveen S., Method and system for controlling data transfers with physical separation of data functionality from address and control functionality in a distributed multi-bus multiprocessor system.
  24. Praveen S. Reddy, Method and system for data bus latency reduction using transfer size prediction for split bus designs.
  25. Deshpande, Sanjay Raghunath; Lenk, Peter Steven; Mayfield, Michael John, Method and system for implementing remstat protocol under inclusion and non-inclusion of L1 data in L2 cache to prevent read-read deadlock.
  26. Deshpande, Sanjay Raghunath; Chan, Tina Shui Wan, Method and system for resolution of transaction collisions to achieve global coherence in a distributed symmetric multiprocessor system.
  27. Beale, Andrew Ward; Paul, Derek William, Method for assigning a multiplicity of interrupt vectors in a symmetric multi-processor computing environment.
  28. Kruse, Robert Earl; Drehmel, Robert Allen, Method, apparatus, and computer program product for controlling data transfer.
  29. Cohn, David L.; Hunt, Guerney D. H.; Moulic, James Randal; Pendarakis, Dimitrios, Mobile device with multiple security domains.
  30. Cohn, David L.; Hunt, Guerney D. H.; Moulic, James Randal; Pendarakis, Dimitrios, Mobile device with multiple security domains.
  31. Hall Christopher M. (Redwood City CA) Phillips Gary D. (San Jose CA) Weinrich David W. (San Jose CA) Salter ; III Robert M. (Saratoga CA), Multiple chip processor architecture with reset intercept circuit.
  32. Cross Charley B. (Billerica MA) Moy Diana Y. (Wayland MA), Multitask subscription data retrieval system.
  33. Vachon Guy (Austin TX), Peripheral I/O bus and programmable bus interface for computer data acquisition.
  34. Sanjay Raghunath Deshpande ; Peter Dau Geiger, Providing global coherence in SMP systems using response combination block coupled to address switch connecting node controllers to memory.
  35. Hall Christopher M. (Redwood City CA) Phillips Gary D. (San Jose CA) Weinrich David W. (San Jose CA), Serial register multi-input multiplexing architecture for multiple chip processor.
  36. Heckel Andreas,DEX ; Rupp Roland,DEX ; Weishaar Christoph,DEX ; Wohnhaas Klaus,DEX, System architecture permitting verified and unverified programs to execute safely on one processor.
  37. Ortega, Juan Gaston, System, method and device to preserve protection communication active during a bypass operation.
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