[특허]Slope etch of polyimide

Slope etch of polyimide 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	B44C-001/22 C03C-015/00 C03C-025/06
출원번호	US-0595229 (1984-03-30)
발명자 / 주소	Almgren Carl W. (Austin TX)
출원인 / 주소	Motorola, Inc. (Schaumburg IL 02)
인용정보	피인용 횟수 : 67 인용 특허 : 4

초록 ▼

A sloped via through polyimide between metal layers is achieved by first sloping a hard mask which overlies the polyimide. Sloped photoresist overlying the hard mask transfers the slope to the hard mask. The sloped hard mask is used to slope the polyimide. Oxide underlying the polyimide is also etch

대표청구항 ▼

In a semiconductor having an insulating layer overlying a metal layer, wherein the insulator comprises an upper oxide layer, an intermediate polyimide layer, and a lower oxide layer in contact with the metal layer, a method for etching a via from an upper surface of the polyimide layer to the metal layer comprising the steps of: applying photoresist; etching an opening from an upper surface of the photoresist layer to the upper oxide layer at a location for forming the via so that an upper surface of the upper oxide layer is exposed at the via location; heating the photoresist to cause a more gradual slope of the photoresist layer from the upper surface of the upper oxide layer at the via location to the upper surface of the photoresist layer; applying reactive ion etchant with a predetermined selectivity between photoresist and oxide to transfer the slope of the photoresist layer to the upper oxide layer at a predetermined ratio; and applying a reactive ion etchant with a predetermined selectivity between oxide and polyimide to transfer the slope of the upper oxide layer to the polyimide layer at a predetermined ratio, whereby the lower oxide layer is simultaneously etched to expose the metal layer at the via location.

이 특허에 인용된 특허 (4)

Pan Alfred I. (San Jose CA), Edge profile control during patterning of silicon by dry etching with CCl₄-O₂ mixtures.
상세보기

Saiki Atsushi (Musahimurayama JPX) Okubo Toshio (Tokyo JPX) Harada Seiki (Hachioji JPX), Method for fabricating semiconductor device and etchant for polymer resin.
상세보기

Belani Jagdish G. (Cupertino CA), Polymeric insulation layer etching process and composition.
상세보기

Stein Leonard (Dewitt NY), Process for selective etching of polymeric materials embodying silicones therein.
상세보기

이 특허를 인용한 특허 (67)

Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
상세보기

Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
상세보기

Andricacos,Panayotis; Cooper,Emanuel Israel; Dalton,Timothy Joseph; Deligianni,Hariklia; Guidotti,Daniel; Kwietniak,Keith Thomas; Steen,Michelle Leigh; Tsang,Cornelia Kang I, Deep filled vias.
상세보기

Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
상세보기

Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
상세보기

Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
상세보기

Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
상세보기

Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
상세보기

Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
상세보기

Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
상세보기

Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
상세보기

Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
상세보기

Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
상세보기

Greenberg, Robert Jay; Humayun, Mark S., Flexible circuit electrode array for improved layer adhesion.
상세보기

Grennberg, Robert Jay; Humayun, Mark S., Flexible circuit electrode array for improved layer adhesion.
상세보기

DeLoach,Juanita; Smith,Brian A., In situ hardmask pullback using an in situ plasma resist trim process.
상세보기

Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
상세보기

Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
상세보기

Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
상세보기

Pham Tuan D. ; Templeton Michael K., Method for fabricating shallow isolation trenches using angular photoresist profiles to create sloped isolation trench w.
상세보기

Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
상세보기

Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
상세보기

Bukhman Yefim (Tempe AZ), Method for forming semiconductor devices.
상세보기

Blosse, Alain P.; Chowdhury, Saurabh Dutta, Method for forming sub-critical dimension structures in an integrated circuit.
상세보기

Kim, Tae-Ho, Method for manufacturing flash memory cell by rie slope etching reflowed photoresist pattern.
상세보기

Wada Osamu (Isehara) Sanada Tatsuyuki (Yokohama) Miura Shuichi (Atsugi) Machida Hideki (Atsugi) Yamakoshi Shigenobu (Ebina) Sakurai Teruo (Sagamihara JPX), Method for producing a monolithically integrated optoelectronic device.
상세보기

Hui, Angela T.; Singh, Bhanwar, Method of creating a smaller contact using hard mask.
상세보기

Hui, Angela T.; Singh, Bhanwar, Method of creating narrow trench lines using hard mask.
상세보기

Shah,Uday; Doyle,Brian S.; Brask,Justin K.; Chau,Robert S., Method of fabricating a multi-cornered film.
상세보기

Nemiroff Michael H. (Del Mar CA), Method of fabricating a tapered via hole in polyimide.
상세보기

Yamamoto Isamu (Hyogo JPX) Fukushima Jiro (Hyogo JPX), Method of forming a passivation film.
상세보기

Auda Bernard (Montlhery FRX), Method of forming a via-hole having a desired slope in a photoresist masked composite insulating layer.
상세보기

Abe Masahiro (Yokohama JPX) Mase Yasukazu (Tokyo JPX), Method of forming holes in semiconductor integrated circuit device.
상세보기

Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
상세보기

Brask, Justin K.; Kavalieros, Jack; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S.; Doyle, Brian S., Methods for patterning a semiconductor film.
상세보기

Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
상세보기

Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
상세보기

Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
상세보기

Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
상세보기

Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
상세보기

Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
상세보기

Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
상세보기

Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
상세보기

Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
상세보기

Hareland,Scott A.; Chau,Robert S.; Doyle,Brian S.; Rios,Rafael; Linton,Tom; Datta,Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
상세보기

Brask, Justin K.; Dovle, Brian S.; Kavalleros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Nonplanar transistors with metal gate electrodes.
상세보기

Uchimura David H. (Chandler AZ), Plasma etch process.
상세보기

Inasaka Jun (Tokyo JPX), Printer circuit and a process for preparing same.
상세보기

Nanda Madan M. (Reston VA) Peterman Steven L. (Manassas VA) Stanasolovich David (Manassas VA), Process for defining vias through silicon nitride and polyimide.
상세보기

Bukhman, Yefim; Thornquist, Steven C., Process for etching tapered polyimide vias.
상세보기

Kavalieros, Jack T.; Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Datta, Suman; Doczy, Mark L.; Metz, Matthew V.; Chau, Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
상세보기

Kavalieros,Jack T.; Brask,Justin K.; Doyle,Brian S.; Shah,Uday; Datta,Suman; Doczy,Mark L.; Metz,Matthew V.; Chau,Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
상세보기

Hills Graham William, Reduced size etching method for integrated circuits.
상세보기

Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
상세보기

Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
상세보기

Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
상세보기

Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
상세보기

Hudait, Mantu K.; Shaheen, Mohamad A.; Chow, Loren A.; Tolchinsky, Peter G.; Fastenau, Joel M.; Loubychev, Dmitri; Liu, Amy W. K., Stacking fault and twin blocking barrier for integrating III-V on Si.
상세보기

Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
상세보기

Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
상세보기

Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
상세보기

Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
상세보기

Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
상세보기

Abrams Allan D. (Essex Junction VT) Bausmith Robert C. (Essex Junction VT) Holland Karey L. (Essex Junction VT) Holland Steven P. (Essex Junction VT), Tailoring of via-hole sidewall slope.
상세보기

Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
상세보기

Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
상세보기

Greenberg, Robert Jay; Humayun, Mark S., Visual prosthesis for improved circadian rhythms and method of improving the circadian rhythms.
상세보기

IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

연합인증

Slope etch of polyimide 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

이 특허에 인용된 특허 (4)

이 특허를 인용한 특허 (67)

관련 콘텐츠

특허 원문 보기

IPC 상위 출원인

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

선택된 텍스트

연합인증

Slope etch of polyimide 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

전체(0) 논문(0) 특허(0) 보고서(0)

전체(0) 논문(0) 특허(0) 보고서(0)

이 특허에 인용된 특허 (4)

이 특허를 인용한 특허 (67)

관련 콘텐츠

특허 원문 보기

IPC 상위 출원인

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

선택된 텍스트