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I/O Storage controller cache system with prefetch determined by requested record\\s position within data block

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/06
  • G06F-013/00
출원번호 US-0270951 (1981-06-05)
발명자 / 주소
  • Dixon Jerry D. (Boca Raton FL) Marazas Gerald A. (Boca Raton FL) Merckel Gerald U. (Delray Beach FL)
출원인 / 주소
  • International Business Machines Corporation (Armonk NY 02)
인용정보 피인용 횟수 : 52  인용 특허 : 12

초록

In a data processing system of the type wherein a host processor transfers data to or from a plurality of attachment devices, a cache memory is provided for storing blocks of data which are most likely to be needed by the host processor in the near future. The host processor can then merely retrieve

대표청구항

A data processing system comprising: a host processor for requesting a record of data; at least one memory unit for storing a plurality of blocks of data each including a sequence of n data records occupying respective positions in said data blocks and consecutively designated R1-Rn including said r

이 특허에 인용된 특허 (12)

  1. Gannon Patrick M. (Poughkeepsie NY) Liptay John S. (Rhinebeck NY), Cache bypass control for operand fetches.
  2. Kobayashi Yoshiuki (Kokubunji JPX) Rokutanda Takashi (Iachikawa JPX), Cache memory control system.
  3. Schmidt Carson T. (Poway CA), Cache memory having a variable data block size.
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  10. Swenson Robert E. (Mendota Heights MN) Sasscer Lawrence D. (Campbell CA) Pusic Vladi (San Jose CA), Hierarchical memory system having cache/disk subsystem with command queues for plural disks.
  11. Duke Alan H. (Pima County AZ) Hartung Michael H. (Pima County AZ) Marschner Frederick J. (Pima County AZ), Method and apparatus for managing data movements from a backing store to a caching buffer store.
  12. Joyce Thomas F. (Burlington MA) Holtey Thomas O. (Newton Lower Falls MA) Panepinto ; Jr. William (Tewksbury MA), Word oriented high speed buffer memory system connected to a system bus.

이 특허를 인용한 특허 (52)

  1. Farber, David A.; Lachman, Ronald D., Accessing data in a data processing system.
  2. Pomerene James H. (Chappaqua NY) Puzak Thomas R. (Cary NC) Rechtschaffen Rudolph N. (Scarsdale NY) So Kimming (Pleasantville NY), Apparatus and method for prefetching subblocks from a low speed memory to a high speed memory of a memory hierarchy depe.
  3. Macon ; Jr. James F. (Boynton Beach FL) Ong Shauchi (San Jose CA) Shih Feng-Hsien W. (Hsien-Chu TWX), Asynchronous read-ahead disk caching using multiple disk I/O processes adn dynamically variable prefetch length.
  4. Zarrinkoub, Houman; Orofino, II, Donald Paul; Ruthramoorthy, Navan, Block processing of input data in graphical programming environments.
  5. Zarrinkoub,Houman; Orofino, II,Donald P.; Ruthramoorthy,Navan, Block processing of input data in graphical programming environments.
  6. Yamamoto Akira,JPX ; Homma Shigeo,JPX ; Asaka Yoshihiro,JPX ; Kuwahara Yoshiaki,JPX ; Kurano Akira,JPX ; Nozawa Masafumi,JPX ; Kitajima Hiroyuki,JPX, Cache control method and apparatus.
  7. Yamamoto,Akira; Homma,Shigeo; Asaka,Yoshihiro; Kuwahara,Yoshiaki; Kurano,Akira; Nozawa,Masafumi; Kitajima,Hiroyuki, Cache control method and apparatus.
  8. Schafer Bruce W. ; Teeters Jeffrey W. ; Chweh Mark C. ; Lee David A. ; O'Connell Daniel P. ; Ramanathan Gowri, Caching apparatus and method for enhancing retrieval of data from an optical storage device.
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  11. Farber, David A.; Lachman, Ronald D., Computer file system using content-dependent file identifiers.
  12. Nay Daniel L. (30147 Via Borica Palos Verdes CA 90274), Computer memory system.
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  18. Cohn Oded (Haifa ILX) Novick Yoram (Haifa ILX) Rodeh Michael (Oshrat ILX) Winokur Alex (Haifa ILX), Data storage apparatus for disk array.
  19. Yamagami Kenji (Kanagawa-ken JPX) Yamamoto Akira (Sagamihara JPX) Satoh Takao (Sagamihara JPX), Data transfer apparatus and method for data processing system.
  20. Hanada Masayuki (Kamakura JPX), Direct memory access controller for reducing access time to transfer information from a disk.
  21. Peddle Charles I. (Scotts Valley CA) Taylor ; Jr. Robert G. (Santa Cruz CA) Masters John R. (Aptos CA) Stark Glenn M. (Santa Cruz CA) Stein Kenneth M. (San Jose CA) Donohue James M. (Los Alamitos CA), Disk drive controller system.
  22. Hronik,Stanley A., Double data rate synchronous SRAM with 100% bus utilization.
  23. Berkowitz Frederick J. (Old Bridge NJ) Brown Sanford S. (River Plaza NJ), Dual mode disk controller.
  24. Farber, David A.; Lachman, Ronald D., Enforcement and policing of licensed content using content-based identifiers.
  25. Rose, Anthony, Filter for a distributed network.
  26. Rose, Anthony, Filter for a distributed network.
  27. Rose, Anthony, Filter for a distributed network.
  28. Mick, John R., Fully synchronous pipelined RAM.
  29. Mick, John R., Fully synchronous pipelined RAM.
  30. Chuang Chiao-Mei (Briarcliff Manor NY) Matick Richard E. (Peekskill NY) Tong Fred T. (Hopewell Junction NY), Functional cache memory chip architecture for improved cache access.
  31. Fukuda Naoyuki (Nara-ken JPX) Yoshida Yukihiro (Ikoma JPX) Kubo Noboru (Yamatokoriyama JPX) Kinosita Kazuo (Tenri JPX), High speed semiconductor memory including a cache-prefetch prediction controller including a register for storing previo.
  32. Esposito Daniel (Lisle IL), I/O interface system using plural buffers sized smaller than non-overlapping contiguous computer memory portions dedicat.
  33. Lusch Robert F. (Vestal NY) Dulzo Jeffrey J. (Columbus OH), LRU error detection using the collection of read and written LRU bits.
  34. Deslippe, Mark H.; Drimusz, Laszlo; Knapp, Herbert C.; Lyons, Kenneth S., Managing an audio network.
  35. McNutt, Bruce, Method and apparatus for providing efficient management of least recently used (LRU) algorithm insertion points corresponding to defined times-in-cache.
  36. Loechel Barbara ; Giovannetti Federico, Method and device using a redundant cache for preventing the loss of dirty data.
  37. Beardsley Brent Cameron ; Benhase Michael Thomas ; Martin Douglas A. ; Morton Robert Louis ; Reid Mark A., Method and system for managing data in cache.
  38. Beardsley Brent Cameron ; Benhase Michael Thomas ; Martin Douglas A. ; Morton Robert Louis ; Reid Mark A., Method and system for managing data in cache using multiple data structures.
  39. Brent Cameron Beardsley ; Michael Thomas Benhase ; Joseph Smith Hyde ; Thomas Charles Jarvis ; Douglas A. Martin ; Robert Louis Morton, Method and system for staging data into cache.
  40. Lautzenheiser Marvin (Springfield VA), Method for operating a cache memory system using a recycled register for identifying a reuse status of a corresponding c.
  41. Dixon Jerry D. (Boca Raton FL) Sotomayor ; Jr. Guy G. (West Palm Beach FL), Method of handling disk sector errors in DASD cache.
  42. Chilton,Kendell A., Methods and apparatus for accessing data elements using improved hashing techniques.
  43. Delaney, William Patrick; Blount, Joseph Russell; DeKoning, Rodney A., Methods and systems for using a write cache in a storage system.
  44. Andrews Lawrence P. (Boca Raton FL) Heath Chester A. (Boca Raton FL) Mead Justin E. (Boca Raton FL) VanDuren Richard G. (Boca Raton FL) Janes Gary A. (Boca Raton FL), Peripheral attachment interface for I/O controller having cycle steal and off-line modes.
  45. Iskiyan James L. (Tucson AZ) Legvold Vernon J. (Tucson AZ) Leung Peter L. H. (Tucson AZ) Martin Guy E. (Tucson AZ), Peripheral subsystem having read/write cache with record access.
  46. Pomerene James H. (Chappaqua NY) Puzak Thomas R. (Yorktown Heights NY) Rechtschaffen Rudolph N. (Scarsdale NY) Sparacio Frank J. (North Bergen NJ), Prefetching system for a cache having a second directory for sequentially accessed blocks.
  47. Smith,Kevin Frank, Prescheduling sequential data prefetches in a preexisting LRU cache.
  48. Orofino, II, Donald Paul, Providing graphic generating capabilities for a model based development process.
  49. Dixon Jerry D. (Boca Raton FL) Farrell Robert H. (Coral Springs FL) Marazas Gerald A. (Boca Raton FL) McNeill ; Jr. Andrew B. (Deerfield Beach FL) Merckel Gerald U. (Delray FL), Redundant page identification for a catalogued memory.
  50. Mick, John R.; Baumann, Mark W., Separate byte control on fully synchronous pipelined SRAM.
  51. Liu Lishing (Pleasantville NY), Sequential prefetching with deconfirmation.
  52. Loafman,Zachary Merlynn, System and method of improving fault-based multi-page pre-fetches.
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