초록 ▼

The present invention relates to a technique for dynamic scheduling of integrated circuit- and packet-switching in accordance with rapidly changing demand in a multibeam satellite switched, time division multiple accessed (SS/TDMA) environment. It is equally applicable to terrestrial communication s

The present invention relates to a technique for dynamic scheduling of integrated circuit- and packet-switching in accordance with rapidly changing demand in a multibeam satellite switched, time division multiple accessed (SS/TDMA) environment. It is equally applicable to terrestrial communication systems, or more broadly to any type of centralized scheduling system involving arbitration of contention for resources among a plurality of users or equipments. All of the scheduling is performed onboard the satellite by a scheduler (6, 8) under the direction of a controller (4). The controller contains all the information related to both circuit requests ([cij]) and packet requests ([pij]) in matrix form, where it constructs these matrices from requests for service from each zone to each zone on a frame-by-frame or possibly less frequent basis, which it receives from the ground via an order-wire facility. The scheduler performs, for each of the slots of a frame, a least-choice assignment of the circuit requests contained in the controller. The scheduler then applies the same least-choice procedure to assign packets to switch positions not already assigned to the circuit traffic. The least-choice assignment yields efficient bandwidth and transponder utilization. Provision is also made for prioritizing or preempting both the circuit and packet traffic employing a movable-boundary or other protocols. At the completion of both the circuit and packet assignments for a particular slot, the controller broadcasts the slot schedule to the earth stations.

대표청구항 ▼

An onboard satellite switching system responsive to both circuit transmission requests and packet transmission requests from a plurality of N separate ground zones for assigning both said circuit and packet requests in each succeeding time slot of a plurality of time slots forming a single time fram

An onboard satellite switching system responsive to both circuit transmission requests and packet transmission requests from a plurality of N separate ground zones for assigning both said circuit and packet requests in each succeeding time slot of a plurality of time slots forming a single time frame, thereby likewise continuously assigning circuit and packet requests in each subsequent time frame, said satellite switching system comprising a controller (4) responsive to said circuit and packet requests on a frame-by-frame basis for first initializing and subsequently terminating the assignment of circuit transmission requests and second initializing and subsequently terminating the assignment of packet transmission requests in each time slot of said single time frame, said controller repeating said initializing and terminating for subsequent time slots forming subsequent time frames; a traffic matrix circuit (6) responsive first to said circuit transmission requests and a plurality of ongoing circuit matrices from said controller for formimg a cost matrix related thereto and responsive second to said packet transmission requests from said controller for forming a cost matrix related thereto; and a least-cost selection circuit (8) responsive first to the cost matrix formed in relation to said circuit transmission requests for selecting a least-cost circuit assignment and using said least-cost circuit assignment to update the cost matrix and relaying said least-cost circuit assignment back to said traffic matrix circuit to be used in updating the circuit traffic matrix and one of a plurality of ongoing circuit matrices, and responsive second to the cost matrix formed in relation to said packet transmission requests for selecting a least-cost packet assignment and using said least-cost packet assignment to update the cost matrix and relaying said least-cost packet assignment back to said traffic matrix circuit to be used in updating the packet traffic matrix.