초록 ▼

A method is given for forming a planarized integrated circuit structure just prior to the formation of metallurgy interconnection lines on the integrated circuit. The method begins with the integrated circuit intermediate product having devices formed therein but before interconnection metallurgy ha

A method is given for forming a planarized integrated circuit structure just prior to the formation of metallurgy interconnection lines on the integrated circuit. The method begins with the integrated circuit intermediate product having devices formed therein but before interconnection metallurgy has been formed on the principal surface of the product. A glass layer is deposited in a non-conformal way onto the principal surface of the integrated circuit. The glass is chosen to have a thermal coefficient of expansion that approximates that silicon and has a softening temperature of less than about 1200°C. The thermal coefficient of expansion approximates that of silicon to reduce stress problems in the integrated circuit structure. The relatively low softening temperature is required for the next step of heating the structure to cause the flow of glass on the surface of the integrated circuit product to fill in the irregularities therein and to thereby planarize the integrated circuit surface. Openings are then formed through the glass down to the device elements of the integrated circuit. The interconnection metallurgy is formed over the surface of the glass and through the openings of the glass to interconnect the device elements of the integrated circuit. The glass may be deposited by various methods which include the sedimentation methods of spraying, centrifuging and spin-on plus sputtering or evaporation methods.

대표청구항 ▼

A method for forming a planarized integrated circuit structure comprising: providing an integrated circuit intermediate product having devices formed therein but before metallurgy has been formed on a principal surface of said product and having a non-planar surface composed of many step-like irregu

A method for forming a planarized integrated circuit structure comprising: providing an integrated circuit intermediate product having devices formed therein but before metallurgy has been formed on a principal surface of said product and having a non-planar surface composed of many step-like irregularities; non-conformally depositing preferentially upon the horizontal surfaces of said irregularities a glass layer having a thermal coefficient of expansion that approximates that of silicon and has a softening temperature of less than about 1200°C. onto said surface; heating the structure to cause the flow of said glass on said surface to fill in the said irregularities therein and to planarize said surface; forming openings through said glass down to the device elements of said integrated circuit; and forming an interconnection metallurgy over and through said openings in said glass to interconnect said device elements of said integrated circuit.