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Booster for transmitting digital signal 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-005/12
  • H03K-006/04
출원번호 US-0397871 (1982-07-13)
발명자 / 주소
  • Uya Masaru (Kadoma JPX)
출원인 / 주소
  • Matsushita Electric Industrial Co., Ltd. (Kadoma JPX 03)
인용정보 피인용 횟수 : 71  인용 특허 : 5

초록

For voltage on a digital signal line whose load capacitance is comparatively large as in a bus line of a CMOS integrated circuit, a detection is made that said voltages enter into a specified voltage range between the ground voltage and the power supply voltage, then based on such detection the volt

대표청구항

A digital signal transmission circuit comprising: a detection means for receiving voltages of a signal line for transmitting digital voltage signals and detecting whether an instantaneous signal line voltage is in a specified voltage range which is between a predetermined first voltage and a predete

이 특허에 인용된 특허 (5)

  1. Tobita Youichi (Itami JPX) Nishizawa ; deceased Hiroshi (late of Osaka JPX by Kazuo Nishizawa ; Emiko Nishizawa ; heirs), Booster circuit.
  2. Pricer, Wilbur D., Controlled power performance driver circuit.
  3. Puri Yogi K. (Vienna VA) Selbo Keith M. A. (Manassas VA), High speed line driver with ground output capability.
  4. Stevens Daniel A. (Arnold MD) Logis ; Jr. John (Severna Park MD) Scheerer Ronald C. (Baltimore MD), Inductive load driver with fast switching capability.
  5. Ishimoto Shoji (Tokyo JPX), Semiconductor circuit.

이 특허를 인용한 특허 (71)

  1. Pitkethly, Scott; Masleid, Robert Paul, Advanced repeater utilizing signal distribution delay.
  2. Pitkethly,Scott; Masleid,Robert Paul, Advanced repeater utilizing signal distribution delay.
  3. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  4. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  5. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  6. Pitkethly,Scott, Advanced repeater with duty cycle adjustment.
  7. Eguchi Takeo (Kanagawa JPX), Apparatus for transmitting digital signal.
  8. Lauffer Donald K. (Poway CA) Rostek Paul M. (San Diego CA) Sani Mehdi H. (La Jolla CA), Assist circuit for a data bus in a data processing system.
  9. Sanwo Ikuo J. (San Marcos CA) Chiu Albert P. (San Diego CA) Kerber William O. (Escondido CA), Assist circuit for improving the rise time of an electronic signal.
  10. Emnett Raymond F. (Colorado Springs CO) Freeman Eugene E. (Colorado Springs CO) Jander Mark J. (Colorado Springs CO) Petty William K. (Colorado Springs CO) Reise Brian G. (Colorado Springs CO) Rishav, CMOS driver for fast single-ended bus.
  11. Trumpp Gerhard (Puchheim DEX), Circuit arrangement for time-regeneration of broadband digital signals.
  12. de Oliveira Antonio M. d. A. (Munich DEX) Staerk Jakob (Karlsfeld DEX), Circuit configuration for accelerated charge reversal of the voltage level of a bus line of an integrated circuit.
  13. Aoyama Keizo (Yamato JPX), Circuit for shaping digital signals in an integrated circuit.
  14. Masleid, Robert Paul; Dholabhai, Vatsal, Circuit with enhanced mode and normal mode.
  15. Masleid, Robert Paul; Kowalczyk, Andre, Circuits and methods for detecting and assisting wire transitions.
  16. Masleid,Robert Paul; Kowalczyk,Andre, Circuits and methods for detecting and assisting wire transitions.
  17. Masleid,Robert Paul; Kowalczyk,Andre, Circuits and methods for detecting and assisting wire transitions.
  18. Masleid, Robert, Circuits, systems and methods relating to a dynamic dual domino ring oscillator.
  19. Masleid,Robert P., Circuits, systems and methods relating to dynamic ring oscillators.
  20. Jason M. Brown ; Steven C. Eplett, Clock input buffer with increased noise immunity.
  21. Masleid, Robert Paul, Column select multiplexer circuit for a domino random access memory array.
  22. Frank Gasparik, Compensating for initial signal interference exhibited by differential transmission lines.
  23. von Sichart Frithjof (Munich DEX), Complementary metal-oxide-semiconductor input circuit.
  24. Masleid, Robert Paul, Configurable delay chain with stacked inverter delay elements.
  25. Masleid,Robert Paul, Configurable delay chain with stacked inverter delay elements.
  26. Masleid, Robert Paul, Configurable delay chain with switching control for tail delay elements.
  27. Masleid, Robert Paul, Configurable tapered delay chain with multiple sizes of delay elements.
  28. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  29. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  30. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  31. Young William R. (Palm Bay FL), Current compensated precharged bus.
  32. Toy,Edmond; De Langen,Klaas Jan, Digital filter circuit and method for blocking a transmission line reflection signal.
  33. Masleid, Robert P, Dynamic ring oscillators.
  34. McMillan, Henry G.; Patel, Pravin; Purrington, Challis L.; Tobin, Gwendolyn R.; West, Christopher C.; Zapata, Ivan R., Fall time accelerator circuit.
  35. Chieli Davide (Milan ITX), High side driver MOS circuit.
  36. Sanwo Ikuo J. (San Marcos CA) Milby Gregory H. (San Diego CA) Kim Moo Y. (Escondido CA), High speed computer data transfer system.
  37. Sanwo Ikuo J. (San Marcos CA) Milby Gregory H. (San Diego CA) Le Quynh-Giao X. (Escondido CA), High speed digital computer data transfer system having reduced bus state transition time.
  38. Bodano,Emanuele; Flaibani,Marco; Garbossa,Cristian, High-side switch with a zero-crossing detector.
  39. Ueno Masaji (Sagamihara JPX) Noine Yasukazu (Chigasaki JPX), In-phase signal output circuit, opposite-phase signal output circuit, and two-phase signal output circuit.
  40. Pfennings Leonardus C. M. G. (Eindhoven NLX) Veendrick Hendrikus J. M. (Eindhoven NLX) Van Zanten Adrianus T. (Eindhoven NLX), Integrated circuit having capacitive process-scatter compensation.
  41. Masleid, Robert P, Inverting zipper repeater circuit.
  42. Masleid, Robert P., Inverting zipper repeater circuit.
  43. Masleid, Robert Paul, Inverting zipper repeater circuit.
  44. Masleid, Robert, Leakage efficient anti-glitch filter.
  45. Masleid,Robert Paul, Leakage efficient anti-glitch filter with variable delay stages.
  46. Wood,Neil E.; Lee,Chan; Kazemzadeh,Abbas, Level shifter circuit.
  47. Takashima Daisaburo,JPX, Logic circuit and semiconductor device using it.
  48. Tallaron Louis (St. Egreve FRX), Logic data transfer bus preloading circuit.
  49. Mohd Bassam J., Noise suppression method and circuits for sensitive circuits.
  50. Yasuda Hiroshi (Tokyo JPX) Ochii Kiyofumi (Yokohama JPX), Output buffer circuit.
  51. Masleid, Robert Paul, Power efficient multiplexer.
  52. Masleid, Robert Paul, Power efficient multiplexer.
  53. Masleid, Robert Paul, Power efficient multiplexer.
  54. Masleid, Robert Paul, Power efficient multiplexer.
  55. Masleid,Robert Paul, Power efficient multiplexer.
  56. Kannegundla Ram (Rochester NY), Remotely driving a CCD.
  57. Masleid, Robert Paul; Dholabhai, Vatsal; Klingner, Christian, Repeater circuit having different operating and reset voltage ranges, and methods thereof.
  58. Masleid,Robert Paul; Dholabhai,Vatsal; Klingner,Christian, Repeater circuit having different operating and reset voltage ranges, and methods thereof.
  59. Masleid,Robert Paul; Dholabhai,Vatsal; Stoiber,Steven Thomas; Singh,Gurmeet, Repeater circuit with high performance repeater mode and normal repeater mode.
  60. Masleid, Robert Paul; Dholabhai, Vatsal, Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability.
  61. Masleid,Robert Paul; Dholabhai,Vatsal, Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability.
  62. Stoiber, Steven T.; Siu, Stuart, Ring based impedance control of an output driver.
  63. Stoiber, Steven T.; Siu, Stuart, Ring based impedance control of an output driver.
  64. Allan James D. (Colorado Springs CO), Source follower CMOS input buffer.
  65. Masleid, Robert P.; Burr, James B., Stacked inverter delay chain.
  66. Masleid,Robert P.; Burr,James B., Stacked inverter delay chain.
  67. Bobba, Sudhakar; Trivedi, Pradeep, Transmission gate based signal transition accelerator.
  68. Manning Troy, Voltage level translator.
  69. Manning Troy, Voltage level translator.
  70. Troy Manning, Voltage level translator.
  71. Troy Manning, Voltage level translator.
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