초록

This circuit provides a minimally sized data transfer buffer interface between two central processing units for transferring data blocks of variable size. The circuit provides an indication to one CPU that the other CPU has received all the data words transmitted.

대표청구항 ▼

A circuit for reliable data word transfer is connected between a first and a second CPU for said data word transfer between said CPUs, said circuit comprising: first and second CPU buses respectively connected between said first and second CPUs and said circuit; buffer means connected to said first

A circuit for reliable data word transfer is connected between a first and a second CPU for said data word transfer between said CPUs, said circuit comprising: first and second CPU buses respectively connected between said first and second CPUs and said circuit; buffer means connected to said first and second CPUs via said first and second buses and said buffer means operated to store and to transmit a number of said data words from said first to said second CPU; said buffer means having a maximum capacity of said data words; first register means connected between said first and second CPUs and operated to store a representation of a particular number of said data words to be transferred from said first to said second CPU; said second CPU operated to receive said stored representation of said particular number of data words; second register means connected between said first and second CPUs and operated to store a representation of the difference between the number of said data words to be transferred and said maximum capacity of said data words of said buffer means; adding means connected to said first and second CPUs and operated to increment said stored representation of said second register means for each data word stored and each data word transmitted by said buffer means; and indication means connected between said second register means and said first CPU, said indication means operated in response to said second register means to provide an acknowledgement signal to said first CPU for indicating said particular number of stored data words of said buffer means are transferred to said second CPU.