초록 ▼

A number of intelligent nodes (bus-interface units-BIUs and memory-control units-MCUs) are provided in a matrix composed of processor buses (105) with corresponding error-reporting and control lines (106); and memory buses (107) with corresponding error-reporting and control lines (108). Each node (

A number of intelligent nodes (bus-interface units-BIUs and memory-control units-MCUs) are provided in a matrix composed of processor buses (105) with corresponding error-reporting and control lines (106); and memory buses (107) with corresponding error-reporting and control lines (108). Each node (100, 101, 102, 103) has means for logging errors and reporting errors on the error-report lines (106, 108). Processor modules (110) and memory modules (112) are each connected to a node which controls access to a common memory bus (107). Each node includes means (a married bit-170 and a shadow bit-172) for marrying modules in pairs such that each module in the pair tracks the operations directed to the module pair, and each module in the pair alternates with the other module in the handling of requests or replies. Each node registers the ID of the other node in a spouse ID register. Comparison logic (162, 164) in each node resets the married bit upon the condition that the node ID (identifying the node at which the error occurred) in an error-report message is equal to the ID stored in the spouse ID register, thus identifying the spouse node (the partner of the node in which the comparison logic is located) as the source of the error. Resetting the married bit splits apart the primary/shadow pair, so that the error-free module takes over and ceases to alternate with its partner.

대표청구항 ▼

For use in a data processing system in which a number of intelligent nodes are provided in a matrix composed of processor buses with corresponding error-reporting and control lines, and memory buses with corresponding error-reporting and control lines, wherein each node has means for logging errors

For use in a data processing system in which a number of intelligent nodes are provided in a matrix composed of processor buses with corresponding error-reporting and control lines, and memory buses with corresponding error-reporting and control lines, wherein each node has means for logging errors and reporting errors on said error-report lines, wherein a primary module is connected to a primary node which controls access to a common memory bus, and wherein a shadow module is connected to a shadow node which controls access to said common memory bus, the combination in each of said primary and shadow nodes comprising: shadow bit means settable to a first state and to a second state; first logic means connected to said processor bus lines for receiving data destined for said common memory bus, said first logic means including means for seting said shadow bit means and said married bit means; married bit means operative when set to a first state for marrying said primary module and said shadow module in a primary/shadow pair such that each module in said primary/shadow pair is activated to receive data directed to said primary/shadow pair; and, second logic means responsive to said shadow bit means and to said married bit means for causing said primary module to be active for at least the first bus transaction and passive for other predetermined bus transactions upon the condition that said shadow bit means is set to said first state and said married bit is set to said first state, said logic means including means for causing said primary module to be passive for the first bus transaction and active for other predetermined bus transactions upon the condition that said shadow bit means is set to said second state and said married bit is set to said second state, such that each module in said primary/shadow pair alternates with the other module in the handling of a predetermined number of memory bus transactions.