초록 ▼

A memory system includes a plurality of memory controllers which connect to a common bus. Each memory controller includes reconfiguration apparatus which enables the controller when faulty to be switched off line and another controller to be substituted in its place so as to maintain system memory c

A memory system includes a plurality of memory controllers which connect to a common bus. Each memory controller includes reconfiguration apparatus which enables the controller when faulty to be switched off line and another controller to be substituted in its place so as to maintain system memory contiguous.

대표청구항 ▼

A data processing system comprising a data processing unit and a memory system including a plurality of addressable memory controllers, each controller for controlling the operation of a memory including a plurality of memory modules included on a corresponding number of daughter boards in response

A data processing system comprising a data processing unit and a memory system including a plurality of addressable memory controllers, each controller for controlling the operation of a memory including a plurality of memory modules included on a corresponding number of daughter boards in response to memory commands, said controllers being coupled in common to a bus for receiving said memory commands and data from said processing unit, each memory command including an address portion including a plurality of address bits coded to specify which one of said controllers is to perform the operation specified by said command and each memory controller including: a reconfiguration control section coupled to said bus, said reconfiguration section for reconfiguring said controller within said system in response to memory commands, said section comprising: register means for storing indications defining the type of controller memory reconfiguration in addition to controller address signals; selectable switching means, said switching means defining the address of said controller within said memory system; output selection means coupled to said register means and to said switching means, said output selection means for providing signals representative of said controller address during a reconfigured mode of operation; and, mode control means coupled to said bus and to said output selection means, said mode control means being switched to a predetermined state in response to a predetermined type of memory command defining a reconfiguration mode of operation for the controller specified by said command address portion, said mode control means when in said predetermined state conditioning said output selection means to apply said controller address signals from said register means as said signals representative of said controller address in lieu of said address from said switching means, enabling reconfiguration of said each memory controller of said plurality of memory controllers within said memory system as required for providing a contiguous addressable memory space.