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A digital computer system including a memory and a processor. The memory operates in response to memory commands received from the processor. Items of data stored in the memory include instructions to which the processor responds. Each instruction contains an operation code which belongs to one of s

A digital computer system including a memory and a processor. The memory operates in response to memory commands received from the processor. Items of data stored in the memory include instructions to which the processor responds. Each instruction contains an operation code which belongs to one of several sets of operation codes. The meaning of a given operation code is determined by the operation code set to which the instruction belongs. Some of the instructions also contain names representing items of data used in the operation specified by the operation code. The processor includes an operation code decoding system which decodes the operation code as required for the instruction set to which it belongs, a name resolution system for deriving the address of the data item represented by a name from the name using an architectural base address contained in the name resolution system, and a control system which controls the operation of the processor. The processor performs a call operation and a return operation. Only the call operation and the return operation may change the current architectural base address. The memory further contains name table entries associated with the names. Each name table entry contains information used by the name resolution system when it resolves a name.

대표청구항 ▼

A digital computer system comprising: (1) memory means for performing memory operations including storing and providing data items in response to memory commands including addresses of said data items, said data items including (A) instructions, each said instruction containing (i) an operation code

A digital computer system comprising: (1) memory means for performing memory operations including storing and providing data items in response to memory commands including addresses of said data items, said data items including (A) instructions, each said instruction containing (i) an operation code of a plurality of said operation codes, each said operation code specifying an operation of a plurality of operations performed by said digital computer system, and each said operation code belonging to one of a plurality of different operation code sets, the operation codes in a given operation code set being definable solely with reference to said given operation code set, and selected ones of said instructions further containing (ii) a name representing an item of data to be used in the operation specified by the operation code in said selected instruction, and (B) sequences of said instructions; and (2) processor means connected to said memory means for performing the operations performed by said system and providing memory commands to said memory means in response to said instructions, said processor means including (A) operation code decoding means for decoding the operation code in an instruction received in said processor as required by the operation code set to which the operation code in said received instruction belongs, (B) name resolution means for receiving the name in said received instruction and for deriving the address for the item of data represented by said received name using a current architectural base address, and (C) control means responsive to said operation code decoding means and to said name resolution means for controlling the operation of said processor means and for providing said memory command including the address provided by said name resolution means to said memory means, and wherein the operation performed by said system include (A) a call operation which suspends the execution of the current sequence of instructions by said processor means and begins the execution of another sequence of instructions, and (B) a return operation which terminates the execution of said another sequence of instructions and resumes said suspended execution, and a currently used architectural base address can only be changed as a result of said call operations and said return operations.