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A pipelined digital processor includes a common data and control bus and a source (100 or 105) of instructions and data words. An arithmetic section (110) processes one data word with another data word through selected processing subsections (112, 115, 116) performing operations according to an expr

A pipelined digital processor includes a common data and control bus and a source (100 or 105) of instructions and data words. An arithmetic section (110) processes one data word with another data word through selected processing subsections (112, 115, 116) performing operations according to an expression, thereby producing a resultant data word and a status signal. A destination (105) receives the resultant data word from the arithmetic section. Control circuits (IR-C) decode a single conditional instruction for controlling performance of a specific condition test during a first subsequent processor cycle (i.e., i+2). The control circuits further decoding another instruction word during the first subsequent processor cycle for controlling all processing sections operations during a second subsequent processor cycle (i.e., i+3). A circuit (215 and 122) compares the status signal with the specific condition information included in the conditional instruction for selectively disabling at least one section while enabling at least one other section of the digital processor during the second subsequent processor cycle.

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1. A digital processor arranged for pipelined data processing operations wherein a data word is processed arithmetically into a resultant data word and a status signal during each processor cycle, the resultant data word being written to a destination; the digital processor comprising a plurality

1. A digital processor arranged for pipelined data processing operations wherein a data word is processed arithmetically into a resultant data word and a status signal during each processor cycle, the resultant data word being written to a destination; the digital processor comprising a plurality of processor sections, including at least an arithmetic, a set register and a write memory section, each processor section being arranged to process one data word while the other processor sections concurrently are processing different data words during every processor cycle; source means for providing a sequence of conditional and unconditional opcode words, a different opcode word controlling processing every processor cycle, each opcode word including a plurality of control fields, a conditional opcode word being designated I i (c,s,t) and an unconditional opcode word being designated I i+1 (l,m, . . . s,t), where i=0,1,2, . . . represents consecutive processor cycles and (i+1), (i+2) . . . represents a consecutive sequence of processor cycles, I i (c) is a conditional control field, I i (s,t) are control fields, I i+1 (l) is an unconditional multiplier control field and I i+1 (m) is an unconditional accumulator control field, each unconditional control field designated (i+1) including information for determining concurrent steps in processing a selected expression of an operand y i+2 ; means (IR-C, IR-S,T, 211, 212, 213, 214, 215, 122 and DECODE F) for decoding the conditional opcode word I i (c,s,t) during a first processor cycle (i+1) of the consecutive sequence of processor cycles and the unconditional opcode word I i+1 (l,m, . . . s,t) during a second and next consecutive processor cycle (i+2) of the consecutive sequence of processor cycles; means for receiving and storing an operand y i+2 during the second processor cycle of the consecutive sequence of processor cycles; and means for executing in the arithmetic, set register and write memory processor sections the processing defined by the unconditional opcode word I i+l (l,m, . . . s,t) during a third processor cycle (i+3) of the consecutive sequence of processor cycles except for the arithmetic section, which is responsive to some of the decoded fields I i+1 (l,m, . . . s,t) during the third processor cycle for processing the operand y i+2 during the third processor cycle if the condition defined by the conditional control field I i (c) is met by the status signal and is disabled for processing the operand y i+2 during the third processor cycle if the condition defined by the conditional control field I i (c) is not met by the status signal. 2. A digital processor arranged for pipelined data processing operations wherein a data word is processed arithmetically into a resultant data word and a status signal during each processor cycle, the resultant data word being written to a destination; the digital processor comprising a plurality of processor sections, including at least an arithmetic, a set register and a write memory sections, each processor section being arranged to process one data word while the other processor section concurrently are processing different data words during every processor cycle; a register; source means for providing a sequence of conditional and unconditional opcode words, a different opcode word controlling processing every processor cycle, each opcode word including a plurality of control fields, a conditional opcode word being designated I i (c,s,t) and an auxiliary opcode word being designated I i+1 (c,s,t), where i=0,1,2 . . . represents consecutive processor cycles and (i+1), (i+2) . . . represents a consecutive sequence of processor cycles, I i (c) is a conditional control field, I i (s,t) are control fields, I i+1 (c) is an auxiliary control field including information for setting the register; means (IR-C, IR-S,T, 211, 212, 213, 214, 215, 122 and 154) for decoding the conditional opcode word I i (c,s,t) during a first processor cycle (i+1) of the consecutive sequence of processor cycles and the auxiliary opcode word I i+1 (c,s,t) during a second and next consecutive processor cycle (i+2) of the consecutive sequence of processor cycles; means for receiving and storing a register control field (XSR,XSL) during the second processor cycle of the consecutive sequence of processor cycles; and means for executing in the arithmetic, set register and write memory processor sections the processing defined by the auxiliary opcode word I i+1 (c,s,t) during a third processor cycle (i+3) of the consecutive sequence of procesor cycles except for the set register processor section, which is responsive to some of the decoded fields I i+1 (c,s,t) during the third processor cycle for setting the register during the third processor cycle if the condition defined by the conditional control field I i (c) is met by the status signal and for not setting the register during the third processor cycle if the condition defined by the conditional control field I i (c) is not met by the status signal. 3. A digital processor arranged for pipelined data processing operations wherein a data word is processed arithmetically into a resultant data word and a status signal during each processor cycle, the resultant data word being written to a destination; the digital processor comprising a plurality of processor sections, including at least an arithmetic, a set register and a write memory sections, each processor section being arranged to process one data word while the other processor section concurrently are processing different data words during every processor cycle; source means for providing a sequence of conditional and normal opcode words, a different opcode word controlling processing every processor cycle, each opcode word including a plurality of control fields, a conditional opcode word being designated I i (c,s,t) and each normal opcode word being designated I i+1 (l,m, . . . s,t), where i=0,1,2, . . . represents consecutive processor cycles and (i+1), (i+2) . . . represents a consecutive sequence of processor cycles, I i (c) is a conditional control field, I i (s,t) are control fields, I i+1 (s) is a normal control field including information identifying a destination for a resultant data word w i+2 ; means (IR-C, IR-S,T, 211, 212, 213, 214, 215, 122 and 221) for decoding the conditional opode word I i (c,s,t) during a first processor cycle (i+1) of the consecutive sequence of processor cycles and the normal opcode word I i+1 (l,m, . . . s,t) during a second and next consecutive processor cycle (i+2) of the consecutive sequence of processor cycles; means for transferring and writing the resultant data word w i+2 during a third processor cycle (i+3) of the consecutive sequence of processor cycles; and means for executing in the arithmetic, set register and write memory processor sections the processing defined by the normal opcode word I i+1 (l,m, . . . s,t) during the third processor cycle (i+3) of the consecutive sequence of processor cycles except for the write memory section, which is responsive to the decoded normal control field I i+1 (s) during the third processor cycle for writing the resultant data word w i+2 to the destination during the third processor cycle if the condition defined by the conditional control field I i (c) is met by the status signal and for disabling writing the resultant data word w i+2 to the destination during the third processor cycle if the condition defined by the conditional control field I i (c) is not met by the status signal.