Circuit arrangement for monitoring speed of a drive motor
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IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G01R-023/09
G01R-023/15
출원번호
US-0410969
(1982-08-24)
우선권정보
DE-0033725 (1981-08-26); DE-0016001 (1982-04-29)
발명자
/ 주소
Moosmann, Helmut
Muller, Rolf
출원인 / 주소
Papst-Motoren GmbH & Co. KG
대리인 / 주소
Fitch, Even, Tabin & Flannery
인용정보
피인용 횟수 :
5인용 특허 :
8
초록▼
A circuit for speed monitoring, particularly for fan drives. A detection device for producing an input signal sequence is provided which has a speed-dependent repetition frequency. The circuit also has a signal converter for converting the input signal sequence into an output signal whose amplitude
A circuit for speed monitoring, particularly for fan drives. A detection device for producing an input signal sequence is provided which has a speed-dependent repetition frequency. The circuit also has a signal converter for converting the input signal sequence into an output signal whose amplitude in a function of the repetition frequency of the input signal sequence. There is also an evaluation circuit, having at least one threshold value element responsive to the output signal of the signal converter and which responds if the output signal amplitude reaches a value corresponding to a drop below a predetermined minimum speed or a rise above a predetermined maximum speed.
대표청구항▼
1. Circuit arrangement for monitoring the speed of a drive motor, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of
1. Circuit arrangement for monitoring the speed of a drive motor, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of the input signal sequence, and an evaluation circuit having at least one threshold value means responsive to the output signal for providing an alarm signal when the amplitude of the output signal reaches a value corresponding to a drop of the motor speed below a predetermined minimum speed, said evaluation circuit having a Predetermined response delay exceeding the acceleration time of the motor to prevent provision of said alarm signal during motor start-up. 2. Circuit arrangement for monitoring the speed of a drive motor, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit having at least one threshold value means responsive to said output signal for providing an alarm signal when the amplitude of said output signal reaches a value corresponding to an increases of the motor speed above a predetermined maximum speed, said evaluation circuit having a predetermined delay exceeding the acceleration time of said motor to prevent the provision of said alarm signal during starting of said motor. 3. A circuit arrangement according to claim 1 or 2, wherein the detection means comprises a pulse shaping stage for producing a rectangular pulse train defining said input signal sequence. 4. A circuit arrangement according to claim 2, wherein the signal converter includes a differentiating stage coupled between the detection means and the output of the signal converter. 5. A circuit arrangement according to claim 4, wherein the signal converter is provided with a first charge storage chargeable through a charging path and with switching means coupled to said charge storage for discharging said charge storage, said switching means being triggered by output signals from the differentiating stage. 6. A circuit arrangement according to claim 5, wherein the charging time constant of the charge storage is a multiple of the discharging time constant thereof. 7. A circuit arrangement according to claim 6, wherein the charge storage is connected in the input circuit of a first threshold va1ue stage of said signal converter. 8. A circuit arrangement according to claim 7, wherein the first threshold value stage is designed to supply output pulses of constant amplitude, the pulse width of said output pulses being a function of the length of time when the voltage across said first charge storage exceeds a predetermined threshold value, and wherein said signal converter further comprises integrator means for integrating the output pulses of the first threshold value stage. 9. A circuit arrangement according to claim 7, wherein a second charge storage chargeable through a further charging path from a d.c. voltage source is discharged by means of the first threshold value stage during the time intervals when the voltage across the first charge storage exceeds a predetermined threshold value. 10. A circuit arrangement according to claim 1 or 2, wherein an RC delay circuit and further threshold value means connected to the output thereof are connected to the output of said at least one threshold value means for suppressing the detection of brief drops below a predetermined speed to be monitored. 11. A circuit arrangement according to claim 1 or 2, further comprising an RC element with resistance means connected between the output of the signal converter and the signal input of the threshold value means and a capacitor connected on one terminal with the signal input of the threshold value means, whereby only after said capacitor connected on one terminal with the signal input has been charged to a predetermined value is the threshold value means responsive to an input signal thereto. 12. A circuit arrangement according to claim 1 or 2, wherein the threshold value means is provided with positive feedback from the output thereof. 13. A circuit arrangement according to claim 11 wherein the other terminal of the capacitor is subject to the action of part of the output signal of the threshold value means. 14. A circuit arrangement according to claim 1 or 2, wherein the evaluation circuit has a latch function. 15. A circuit arrangement according to claim 14, wherein a storage means is Provided for executing said latdh function by storing said alarm signal. 16. A circuit arrangement according to claim 15, wherein said storage means comprises a resettable digital storage device. 17. A circuit arrangement according to claim 16, wherein the resettable digital storage device has a comparator with feed-back means by which the comparator is locked in the set state following setting and is adapted to be unlocked by external action only. 18. A circuit arrangement according to claim 17, wherein the feed-back means of said digital storage device is connected to an input of the threshold value means for also locking said threshold value means in response to said alarm signal. 19. A circuit arrangement according to claim 15, wherein the threshold value means is itself constructed as the storage means. 20. A circuit arrangement according to claim 19, wherein said threshold value means has associated thereto locking means which can only be unlocked by external action. 21. A circuit arrangement according to claim 20, wherein a diode is connected between the outputs of the signal converter and the threshold value means. 22. A circuit arrangement according to claim 1 or 2, wherein its power supply is insulated from the power supply of the motor. 23. A circuit arrangement according to claim 22, wherein the evaluation circuit is connected to the output of the signal converter via an optoelectronic coupler. 24. A circuit arrangement according to claim 2, wherein the active components of the pulse shaping stage, the signal converter and the evaluation circuit are formed by an integrated quadruple comparator circuit. 25. A circuit arrangement according to claim 1 or 2, wherein the detection device has a sensor coil which is positioned as an additional winding on at least one stator pole of an electric motor to be monitored. 26. A circuit arrangement according to claim 1 or 2, wherein the detection device has a sensor coil with an associated sensor magnet disposed such that a ferro-magnetic part of the motor to be monitored moves past it. 27. A circuit arrangement for speed monitoring, particularly for fan drives, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit having a predetermined response delay, said evaluation circuit including at least one threshold value means which is responsive to said output signal and which responds if the amplitude of said output signal reaches a value corresponding to a drop of the monitored speed below a predetermined minimum speed, and an RC circuit including resistance means connected between the output of the signal converter and the signal input of said threshold value means and a capacitor, one terminal of said capacitor being connected with the signal input of said threshold value means and the other terminal of said capacitor being subject to the action of part of the output signal of said threshold value means, whereby said threshold value means is prevented from responding to an input signal applied thereto until the voltage across said capacitor exceeds a predetermined value thereby to provide for said response delay. 28. A circuit arrangement for speed monitoring, particularly for fan drives, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit having at least one threshold value means which is responsive to said output signal and which responds by providing a recognition signal if the amplitude of said output signal reaches a value corresponding to a drop below a predetermined minimum speed, said evaluation circuit having a latch function for said recognition signal. 29. A circuit arrangement for speed monitoring, particularly for fan drives, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit including at least one threshold value means which is responsive to said output signal and which responds if the amplitude of said output signal reaches a value corresponding to a drop of the monitored speed below a predetermined minimum speed, said evaluation circuit being provided with its own power supply. 30. A circuit arrangement for speed monitoring, particularly for fan drives, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit having a predetermined response delay, said evaluation circuit including at least one threshold value means which is responsive to said output signal and which responds if the amplitude of said output signal reaches a value corresponding to an increase of the monitored speed over a predetermined maximum speed, and an RC circuit including resistance means connected between the output of the signal converter and the signal input of said threshold value means and a capacitor, one terminal of said capacitor being connected with the signal input of said threshold value means and the other terminal of said capacitor being subject to the action of part of the output signal of said threshold value means, whereby said threshold value means is prevented from responding to an input signal applied thereto until the voltage across said capacitor exceeds a predetermined value thereby to provide for said response delay. 31. A circuit arrangement for speed monitoring, particularly for fan drives, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit having at least one threshold value means which is responsive to said output signal and which responds by providing a recognition signal if the amplitude of said output signal reaches a value corresponding to an increase over a predetermined maximum speed, said evaluation circuit having a latch function for said recognition signal. 32. A circuit arrangement for speed monitoring, particularly for fan drives, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit including at least one threshold value means which is responsive to said output signal and which responds if the amplitude of said output signal reaches a value corresponding to an increase of the monitored speed over a predetermined maximum speed, said evaluation circuit being provided with its own power supply.
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이 특허에 인용된 특허 (8)
Schmidt ; Peter, Clutch apparatus for generating a pulse train.
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