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A multiple phase electronic inverter circuit includes a transistor bridge output circuit having a pair of series connected transistors in each output phase leg connected between a pair of conductors for supplying direct current to opposite ends of the phase leg with a connection point between the tr

A multiple phase electronic inverter circuit includes a transistor bridge output circuit having a pair of series connected transistors in each output phase leg connected between a pair of conductors for supplying direct current to opposite ends of the phase leg with a connection point between the transistors of each phase leg serving as an output power pole. A waveform pattern generator generates a transistor switching pattern which causes the transistors to alternate between two complementary operating modes such that one transistor in each phase leg functions in a communication mode and the other transistor in that phase leg functions in a non-commutation mode. By switching between the two operating modes, saturation of controlled current feedback transformers in the base drive circuit of each transistor is prevented.

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An electronic inverter comprising: a pair of DC link conductors; a plurality of output power pole terminals; an output circuit having a plurality of branch circuits connected in parallel between said DC link conductors, each of said branch circuits including a pair of switching transistors connected

An electronic inverter comprising: a pair of DC link conductors; a plurality of output power pole terminals; an output circuit having a plurality of branch circuits connected in parallel between said DC link conductors, each of said branch circuits including a pair of switching transistors connected in series wherein each output power pole is connected to a point between the transistors in one of said branch circuits; a plurality of drive circuits for supplying base current to each of said transistors, each drive circuit including a controlled current feedback transformer which uses the collector current of the associated switching transistor to supply the required base drive current; and means for generating a switching pattern waveform for controlling the duty cycle of each of said switching transistors, said switching pattern alternating between a logic high level and a logic low level wherein each successive logic level lasts for a time which is less than the saturation time of the controlled current feedback transformer in each drive circuit while the period of the fundamental frequency of the inverter output voltage is greater than the saturation time of the controlled current feedback transformer in each drive circuit.