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Integrated circuit multilevel interconnect system and method 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G03C-005/00
출원번호 US-0649531 (1984-09-11)
발명자 / 주소
  • Chiang Ping-Wang (Los Gatos CA)
출원인 / 주소
  • Amdahl Corporation (Sunnyvale CA 02)
인용정보 피인용 횟수 : 27  인용 특허 : 6

초록

A process for forming on a substructure a plural layer, conductor interconnect pattern consisting of a plurality of successively formed, substantially planar, composite layers of insulating material and conductive material with said insulating material on each layer defining a pattern of regions fil

대표청구항

A process for forming an integrated circuit on a substructure having a substantially varying surface topology with surface hills and valleys including the step of forming a plural layer, conductor interconnect pattern and including the step of forming a plurality of successive, substantially planar,

이 특허에 인용된 특허 (6)

  1. Gwozdz, Peter S., Method for interconnecting metallic layers.
  2. Mitsumori Ken\ichi (Miyagi JPX) Aikawa Kazuo (Kashimadai JPX), Method of fabricating a circuit board and circuit board provided thereby.
  3. Anantha Narasipur G. (Hopewell Junction NY) Bhatia Harsaran S. (Wappingers Falls NY) Lechaton John S. (Wappingers Falls NY) Walsh James L. (Hyde Park NY), Method of planarizing silicon dioxide in semiconductor devices.
  4. Abrahamovich, Karen M.; Hamel, Clifford J.; Payne, Edward H.; Weed, Dean R., Methods of simultaneous contact and metal lithography patterning.
  5. Chang Kenneth (Hopewell Junction NY) Chiu George T. (Wappingers Falls NY) Hoeg ; Jr. Anthony (Cary NC) Lee Linda H. (Poughkeepsie NY), Planar metal interconnection system and process.
  6. Feng Bai-Cwo (Wappingers Falls NY), Planarization of integrated circuit surfaces through selective photoresist masking.

이 특허를 인용한 특허 (27)

  1. Choi,Byung Jin; Meissl,Mario J.; Sreenivasan,Sidlagata V.; Watts,Michael P. C., Formation of discontinuous films during an imprint lithography process.
  2. Sreenivasan, Sidlgata V.; Choi, Byung-Jin, Imprinting of partial fields at the edge of the wafer.
  3. Stolmeijer Andre, Interconnect scheme for integrated circuits.
  4. Choi, Byung-Jin; Sreenivasan, Sidlgata V., Method and system for double-sided patterning of substrates.
  5. Merenda Pierre (Aix en Provence FRX) Chantraine Philippe (Neuilly sur Seine FRX) Lambert Daniel (Juvisy sur Orge FRX), Method for forming a multilayered metal network for bonding components of a high-density integrated circuit using a spin.
  6. Philippe Martin FR, Method for producing contact between two circuit layers separated by an insulating layer.
  7. Sreenivasan, Sidlgata V.; McMackin, Ian M.; Melliar-Smith, Christopher Mark; Choi, Byung-Jin, Method of concurrently patterning a substrate having a plurality of fields and a plurality of alignment marks.
  8. Kira Toru (Tenri JPX) Yamasaki Hidenori (Yamatokoriyama JPX) Yoshikawa Mitsuhiko (Ikoma JPX), Method of manufacturing thin film magnetic head.
  9. Sreenivasan, Sidlgata V.; Watts, Michael P. C., Method to arrange features on a substrate to replicate features having minimal dimensional variability.
  10. Sreenivasan, Sidlgata V.; Schumaker, Philip D., Patterning a plurality of fields on a substrate to compensate for differing evaporation times.
  11. Choi, Byung-Jin; Sreenivasan, Sidlgata V., Patterning substrates employing multiple chucks.
  12. Elkins Patricia C. (Long Beach CA) Chan Yau-Wai D. (Fullerton CA) Chi Keh-Fei C. (Garden Grove CA) Reinhardt Karen A. (Tustin CA) Tang Rebecca Y. (Anaheim CA) Zwingman Robert L. (Walnut CA), Planarization process for double metal MOS using spin-on glass as a sacrificial layer.
  13. Smith Gregory C. ; Bonifield Thomas D., Planarized selective tungsten metallization system.
  14. Schmid, Gerard M.; Stacey, Nicholas A; Resnick, Douglas J.; Voisin, Ronald D.; Myron, Lawrence J., Self-aligned process for fabricating imprint templates containing variously etched features.
  15. Wu, Cheng-Tsung; Lin, Shin-Cheng; Ho, Yu-Hao; Lin, Wen-Hsin, Semiconductor structure having conductive layer overlapping field oxide.
  16. Sreenivasan, Sidlgata V.; Choi, Byung J.; Schumaker, Norman E.; Voisin, Ronald D.; Watts, Michael P. C.; Meissl, Mario J., Step and repeat imprint lithography processes.
  17. GanapathiSubramanian, Mahadevan; Choi, Byung-Jin; Miller, Michael N.; Stacey, Nicholas A., Technique for separating a mold from solidified imprinting material.
  18. Selinidis, Kosta S.; Choi, Byung-Jin; Schmid, Gerard M.; Thompson, Ecron D.; McMackin, Ian Matthew, Template having alignment marks formed of contrast material.
  19. Sreenivasan, Sidlgata V.; Schumaker, Philip D.; McMackin, Ian M., Tessellated patterns in imprint lithography.
  20. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  21. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  22. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  23. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  24. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  25. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  26. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  27. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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