초록 ▼

The cache reload time in small computer systems is improved by using a distributed cache located on the memory chips. The large bandwidth between the main memory and cache is the usual on-chip interconnecting lines which avoids pin input/output problems. This distributed cache is achieved by the use

The cache reload time in small computer systems is improved by using a distributed cache located on the memory chips. The large bandwidth between the main memory and cache is the usual on-chip interconnecting lines which avoids pin input/output problems. This distributed cache is achieved by the use of communicating random access memory chips of the type incorporating a primary port (10) and a secondary port (14). Ideally, the primary and secondary ports can run totally independently of each other. The primary port functions as in a typical dynamic random access memory and is the usual input/output path for the memory chips. The secondary port, which provides the distributed cache, makes use of a separate master/slave row buffer (15) which is normally isolated from the sense amplifier/latches. Once this master/slave row buffer is loaded, it can be accessed very fast, and the large bandwidth between the main memory array and the on-chip row buffer provides a very fast reload time for a cache miss.

대표청구항 ▼

A distributed, on-chip cache comprising a secondary row port buffer on a plurality of dynamic random access memory chips, each of said memory chips comprising a primary port for access to a storage array on the chip, said secondary row port buffer, and isolation means for providing a normally isolat

A distributed, on-chip cache comprising a secondary row port buffer on a plurality of dynamic random access memory chips, each of said memory chips comprising a primary port for access to a storage array on the chip, said secondary row port buffer, and isolation means for providing a normally isolated connection between said secondary row port buffer and said storage array, said secondary row port buffer comprising a master register, a slave register, and parallel input/output driver means for providing access to said slave register, said master register being loaded from said storage array through said isolation means and subsequently when said secondary row port buffer is isolated from said storage array by said isolation means, said slave register being loaded from said master register.