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Microword control system utilizing multiplexed programmable logic arrays 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/28
출원번호 US-0350660 (1982-02-22)
발명자 / 주소
  • Moore Victor S. (Pompano Beach FL) Veneski Gerard A. (Boca Raton FL) Parker Tony E. (Boca Raton FL) Rhodes
  • Jr. Joseph C. (Boca Raton FL) Kraft Wayne R. (Coral Springs FL) Stahl
  • Jr. William L. (Co
출원인 / 주소
  • International Business Machines Corp. (Armonk NY 02)
인용정보 피인용 횟수 : 31  인용 특허 : 4

초록

A microword control system is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword control system includes a plurality of programmable logic array mechanisms responsive to the processor

대표청구항

In a microprogrammed data processor wherein a sequence of microwords are used to control the execution of each processor instruction, an improved microword control system comprising: a plurality of programmable logic array mechanisms responsive to the processor instruction to be executed for individ

이 특허에 인용된 특허 (4)

  1. Bernstein David H. (Ashland MA) Carberry Richard A. (Cupertino CA) Druke Michael B. (Chelmsford MA) Gusowski Ronald I. (Westboro MA), Data processing system utilizing a unique two-level microcoding technique for forming microinstructions.
  2. Druke Michael B. (Chelmsford MA) Feaver Richard L. (Sunnyvale CA) Kosior Stefan (Chepachet RI), External microcode operation in a multi-level microprocessor.
  3. Tutt William E. (Boca Raton FL) Wyatt Virgil D. (Light House Point FL), Overlapped and interleaved control store with address modifiers.
  4. Reyling ; Jr. George F. (Sunnyvale CA) Beall William H. (Palo Alto CA), Programmable logic array control section for data processing system.

이 특허를 인용한 특허 (31)

  1. Rohe,Andre; Teig,Steven, Concurrent optimization of physical design and operational cycle assignment.
  2. Schmit, Herman; Huang, Randy Renfu, Configurable IC having a routing fabric with storage elements.
  3. Teig, Steven, Configurable IC having a routing fabric with storage elements.
  4. Teig, Steven; Schmit, Herman; Huang, Randy Renfu, Configurable IC having a routing fabric with storage elements.
  5. Teig, Steven; Schmit, Herman; Redgrave, Jason, Configurable IC having a routing fabric with storage elements.
  6. Teig, Steven; Schmit, Herman; Redgrave, Jason; Chandra, Vikas, Configurable IC with interconnect circuits that also perform storage operations.
  7. Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert A. (San Jose CA) Wong Jennifer (Fremont CA), Configuration modes for a time multiplexed programmable logic device.
  8. DeHon Andre ; Bolotski Michael ; Knight ; Jr. Thomas F., DPGA-coupled microprocessors.
  9. Morinaga Shigeki (Hitachi JPX) Watabe Mitsuru (Hitachi JPX), Data conflict prevention for processor with input/output device.
  10. Pugh, Daniel J.; Caldwell, Andrew, IC that efficiently replicates a function to save logic and routing resources.
  11. Stephen M. Trimberger ; Richard A. Carberry ; Robert Anders Johnson ; Jennifer Wong, Method of time multiplexing a programmable logic device.
  12. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Method of time multiplexing a programmable logic device.
  13. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Method of time multiplexing a programmable logic device.
  14. Moore, William P.; Ventrone, Sebastian T., Method of updating a semiconductor design.
  15. Moore William P. ; Ventrone Sebastian T., Microprocessor including controller for reduced power consumption and method therefor.
  16. Moore,William P.; Ventrone,Sebastian T., Microprocessor including microcode unit that only changes the value of control signals required for the current cycle operation for reduced power consumption and method therefor.
  17. Rohe, Andre; Teig, Steven, Operational cycle assignment in a configurable IC.
  18. Rohe, Andre; Teig, Steven, Operational cycle assignment in a configurable IC.
  19. Rohe, Andre; Teig, Steven, Operational cycle assignment in a configurable IC.
  20. Rohe, Andre; Teig, Steven, Operational cycle assignment in a configurable IC.
  21. Rohe,Andre; Teig,Steven, Operational cycle assignment in a configurable IC.
  22. Rohe, Andre; Teig, Steven; Schmit, Herman; Redgrave, Jason; Caldwell, Andrew, Operational time extension.
  23. Rohe, Andre; Teig, Steven; Schmit, Herman; Redgrave, Jason; Caldwell, Andrew, Operational time extension.
  24. Concha Fernando (Boca Raton FL) Loffredo John M. (Deerfield Beach FL), PLA microcode controller.
  25. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device including configuration data or user data memory slices.
  26. Caldwell, Andrew; Teig, Steven, Sequential delay analysis by placement engines.
  27. Sawase, Terumi; Noguchi, Kouki; Nakamura, Hideo; Akao, Yasushi; Baba, Shiro; Hagiwara, Yoshimune, Single-chip microcomputer including non-volatile memory elements.
  28. Sawase Terumi,JPX ; Noguchi Kouki,JPX ; Nakamura Hideo,JPX ; Akao Yasushi,JPX ; Baba Shiro,JPX ; Hagiwara Yoshimune,JPX, Single-chip semiconductor integrated circuit device and microcomputer integrated on a semiconductor chip.
  29. Teig, Steven; Caldwell, Andrew, Timing operations in an IC with configurable circuits.
  30. Redgrave, Jason, User registers implemented with routing circuits in a configurable IC.
  31. Redgrave, Jason, Users registers implemented with routing circuits in a configurable IC.
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