초록 ▼

A two read-port, two write-port register file on a single integrated circuit chip provides dual read/write access via either an “A”-side or a “B”-side of a single array of addressable registers. Separate on-chip “A”-side and “B”-side multiplexers permit reading or writing of an independently address

A two read-port, two write-port register file on a single integrated circuit chip provides dual read/write access via either an “A”-side or a “B”-side of a single array of addressable registers. Separate on-chip “A”-side and “B”-side multiplexers permit reading or writing of an independently addressed register according to the phase of the “A”-side or “B”-side clock. Writing can be selectively effected to either a high-order and/or a low-order byte within the addressed register. Unidirectional busses connect each register to each of the four ports. The register can be expanded to provide a four read-port, two write-port register file such as is required for the parallel computation of addresses and data.

대표청구항 ▼

A dual-access single-chip integrated circuit digital storage device having at least two input port means for receiving plural-bit data words and at least two output port means for generating plural-bit words, comprising: random access memory (RAM) comprising a plurality of addressable plural-bit sto

A dual-access single-chip integrated circuit digital storage device having at least two input port means for receiving plural-bit data words and at least two output port means for generating plural-bit words, comprising: random access memory (RAM) comprising a plurality of addressable plural-bit storage registers each connected to each said input port means by unidirectional busses; on-chip addressing means responsive to a first and second storage register address signal and a first and second bi-state read/write signal for coupling said storage register having said first address to a first predetermined one of said input port means or to a first predetermined one of said output port means depending on the state of said first read/write signal and for coupling said storage register having said second address to a second predetermined one of said input port means or to second predetermined one of said output port means depending on the state of said second read/write signal; and on-chip multiplex means connected to said addressing means and receiving at a first input a read address signal and at a second input a write address signal responsive to a bi-phase clock signal for selectively communicating to said addressing means said read address signal during the application of a predetermined one of said clock phase signal and said write address signal during the application of a predetermined second of said clock phase signal, and whereby, the plural-bit contents of said RAM registers selected by said first and second address signals can be communicated to a predetermined one of said at least two input port means; and whereby, during the application of said predetermined one of said clock phase signal the contents of said storage register having said write address is replaced by the plural-bit data word received at a predetermined one of said input port means and during the application of said predetermined second of said clock phase signal the contents of said storage register having said read address is conducted to a predetermined one of said output port means.