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Process of making a semiconductor device having parallel leads directly connected perpendicular to integrated circuit la 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/02
  • H01L-023/48
  • H01L-023/28
출원번호 US-0655476 (1984-09-27)
발명자 / 주소
  • Brown Candice H. (San Jose CA)
출원인 / 주소
  • Advanced Micro Devices, Inc. (Sunnyvale CA 02)
인용정보 피인용 횟수 : 53  인용 특허 : 5

초록

An improved package for a semiconductor device comprises an integrated circuit die and a mounting package having an array of parallel leads which directly connect perpendicular to the die. The process for making the package comprises forming an array of parallel, spaced apart, conductor pins; bondin

대표청구항

A method for making a semiconductor device comprising an integrated circuit die and a mounting package including leads to interconnect the die with external electrical components, said process comprising: (a) forming an array of parallel conductor pins equidistantly spaced apart hexagonal to one ano

이 특허에 인용된 특허 (5)

  1. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
  2. Butner Karl (Freising DEX) Hehnen Josef (Neufahrn DEX) Rudiger Reiner (Freising DEX), Encapsulated power semiconductor device with single piece heat sink mounting plate.
  3. Pommerrenig, Dieter H., Large scale integrated focal plane.
  4. Moser Floyd R. (South Burlington VT) Noth Richard W. (Underhill VT), Method of sealing an electronic module in a cap.
  5. Desai Kamalesh S. (Wappingers Falls NY) Eggerding Carl L. (Wappingers Falls NY) Ferrante John A. (Sherman CT) Ricci Raymond (Wappingers Falls NY) Urfer Ernest N. (Hopewell Junction NY), Process and structure for minimizing delamination in the fabrication of multi-layer ceramic substrate.

이 특허를 인용한 특허 (53)

  1. Crane ; Jr. Stanford W. ; Larcomb Daniel ; Krishnapura Lakshminarasimha, Apparatus for and method of manufacturing a semiconductor die carrier.
  2. Crane, Jr., Stanford W.; Larcomb, Daniel; Krishnapura, Lakshminarasimha, Apparatus for and method of manufacturing a semiconductor die carrier.
  3. Crane, Jr., Stanford W.; Portuondo, Maria M.; Erickson, Willard; Bizzarri, Maurice, Backplane system having high-density electrical connectors.
  4. Crane, Jr.,Stanford W., Backplane system having high-density electrical connectors.
  5. Distefano Thomas H., Bonding lead structure with enhanced encapsulation.
  6. Nakamura Yoshifumi,JPX ; Bessho Yoshihiro,JPX ; Itagaki Minehiro,JPX, Chip carrier.
  7. Yoshifumi Nakamura JP; Yoshihiro Bessho JP; Minehiro Itagaki JP, Chip carrier and method of manufacturing and mounting the same.
  8. Inoue Tatsuo,JPX, Chip size package.
  9. Crane ; Jr. Stanford W. ; Portuondo Maria M. ; Erickson Willard ; Bizzarri Maurice, Computer having a high density connector system.
  10. Crane ; Jr. Stanford W. ; Portuondo Maria M. ; Erickson Willard ; Bizzarri Maurice, Computer system having a modular architecture.
  11. Crane ; Jr. Stanford W. ; Portuondo Maria M. ; Cruz Edward V. ; Razo Vincent R. ; Fynn Shaun, Computer system having a motorized door mechanism.
  12. Crane ; Jr. Stanford W. (Boca Raton FL) Portuondo Maria M. (Boca Raton FL) Cruz Edward V. (Newbury Park CA) Razo Vincent R. (Granada Hills CA) Fynn Shaun (West Hollywood CA), Computer with two fans and two air circulation areas.
  13. Sokolovsky Paul J. (Sunnyvale CA) Hunter John (San Jose CA) Hayward James L. (Sunnyvale CA), Electrical connections via unidirectional conductive elastomer for pin carrier outside lead bond.
  14. Akram, Salman; Hembree, David R.; Farnworth, Warren M., Electrical connector.
  15. David R. Hembree, Electrical connector.
  16. Crane ; Jr. Stanford W., Electrical interconnect system with wire receiving portion.
  17. Hajime Matsuzawa JP; Koetsu Tamura JP, Electronic device structure capable of preventing malfunction caused by electromagnetic wave coming from outside.
  18. Crane ; Jr. Stanford W., High-density electrical interconnect system.
  19. Crane ; Jr. Stanford W., High-density electrical interconnect system.
  20. Crane ; Jr. Stanford W. (3934 NW. 57th St. Boca Raton FL 33496), High-density electrical interconnect system.
  21. Crane, Jr., Stanford W., High-density electrical interconnect system.
  22. Palmer Mark J. (Phoenix AZ), Integrated circuit package that has a plurality of staggered pins.
  23. Cohn Charles (Wayne NJ), Integrated circuit package using plastic encapsulant.
  24. Mosley Joseph M. ; Portuondo Maria M. ; Taylor Drew L., Low profile semiconductor die carrier.
  25. Pai, Deepak K., Method and apparatus to compliantly interconnect commercial-off-the-shelf chip scale packages and printed wiring boards.
  26. Yoshifumi Nakamura JP; Yoshihiro Bessho JP; Minehiro Itagaki JP, Method for manufacturing electronic device with resin layer between chip carrier and circuit wiring board.
  27. Akram, Salman; Farnworth, Warren M., Method of forming recessed socket contacts.
  28. Farnworth, Warren M., Method of forming socket contacts.
  29. Farnworth,Warren M., Method of forming socket contacts.
  30. Crane ; Jr. Stanford W. ; Portuondo Maria M., Method of manufacturing a semiconductor chip carrier.
  31. Higashida,Takaaki; Kumagai,Koichi; Matsuo,Takahiro, Method of manufacturing a semiconductor element-mounting board.
  32. Akram, Salman; Hembree, David R.; Farnworth, Warren M., Methods for electrical connector.
  33. Akram, Salman; Hembree, David R.; Farnworth, Warren M., Methods for the fabrication of electrical connectors.
  34. Crane, Jr., Stanford W., Modular architecture for high bandwidth computers.
  35. Wen-chou Vincent Wang ; Thomas J. Massingill ; Yasuhito Takahashi ; Lei Zhang, Modules with pins and methods for making modules with pins.
  36. Chong Kwang Yoon KR; Chan Keun Kim KR, Multiple line grid array package.
  37. Crane ; Jr. Stanford W. ; Krishnapura Lakshminarasimha ; Li Yun, Open-cavity semiconductor die package.
  38. Crane, Jr., Sanford W.; Krishnapura, Lakshminarasimha; Li, Yun, Open-cavity semiconductor die package.
  39. Stanford W. Crane, Jr. ; Lakshminarasimha Krishnapura ; Yun Li, Open-cavity semiconductor die package.
  40. Crane ; Jr. Stanford W. ; Portuondo Maria M. ; Erickson Willard ; Bizzarri Maurice, Passive backplane capable of being configured to a variable data path width corresponding to a data size of the pluggab.
  41. Crane, Jr., Stanford W.; Portuondo, Maria M., Prefabricated semiconductor chip carrier.
  42. Crane, Jr., Stanford W.; Portuondo, Maria M., Prefabricated semiconductor chip carrier.
  43. Stanford W. Crane, Jr. ; Maria M. Portuondo, Prefabricated semiconductor chip carrier.
  44. Akram,Salman; Farnworth,Warren M., Process of forming socket contacts.
  45. Crane ; Jr. Stanford W. ; Portuondo Maria M., Semiconductor chip carrier affording a high-density external interface.
  46. Crane, Jr., Stanford W.; Portuondo, Maria M., Semiconductor chip carrier affording a high-density external interface.
  47. Crane, Jr.,Stanford W.; Portuondo,Maria M., Semiconductor chip carrier affording a high-density external interface.
  48. Crane ; Jr. Stanford W. ; Portuondo Maria M., Semiconductor chip carrier including an interconnect component interface.
  49. Mosley Joseph M. ; Portuondo Maria M., Semiconductor die carrier having a dielectric epoxy between adjacent leads.
  50. Crane ; Jr. Stanford W. ; Krishnapura Lakshminarasimha, Semiconductor die package for mounting in horizontal and upright configurations.
  51. Yoon, In Sang; Bae, JoHyun; Yang, DeokKyung, Semiconductor packaging system with an aligned interconnect and method of manufacture thereof.
  52. Sher Joseph C. ; Ma Manny K. F. ; Casper Stephen L., Staggered contact placement on CMOS chip.
  53. Brown Candice H. (San Jose CA), Test fixture capable of electrically testing an integrated circuit die having a planar array of contacts.
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