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Method of manufacturing a semiconductor device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0798728 (1985-11-19)
우선권정보 JP-0096126 (1981-05-31)
발명자 / 주소
  • Taguchi Shinji (Yokohama JPX) Matsumura Homare (Kawasaki JPX) Maeguchi Kenji (Yokohama JPX)
출원인 / 주소
  • Kabushiki Kaisha Toshiba (Kawasaki JPX 03)
인용정보 피인용 횟수 : 31  인용 특허 : 3

초록

A method of manufacturing a semiconductor device is disclosed. In the manufacturing method, an impurity diffusion layer as a first interconnection layer is formed on a semiconductor substrate. Then, an aluminum layer as a second interconnection layer is formed on the semiconductor substrate with an

대표청구항

A method for connecting first and second interconnection layers of an integrated circuit device comprising the steps of: forming said first interconnection layer of a predetermined pattern, forming a first insulation film on said first interconnection layer, forming said second interconnection layer

이 특허에 인용된 특허 (3)

  1. Hall John H. (Saratoga CA), High temperature refractory metal contact assembly and multiple layer interconnect structure.
  2. Chang Kenneth (Hopewell Junction NY) Cosman David C. (Newburgh NY) Gartner Helmut M. (Wappingers Falls NY) Hoeg ; Jr. Anthony J. (Wappingers Falls NY), Method of forming thin film interconnection systems.
  3. Swartz Robert G. (Highlands NJ), Microwave transistor.

이 특허를 인용한 특허 (31)

  1. Pfiester James R. (Austin TX), Contact structure and method.
  2. Roberts Martin C. ; Tang Sanh D., Dual poly integrated circuit interconnect.
  3. Mastroianni Sal T. (Tempe AZ), Fusible link with built-in redundancy.
  4. Roberts,Martin C.; Tang,Sanh D., Integrated circuit interconnect.
  5. Roberts,Martin C.; Tang,Sanh D., Integrated circuit using a dual poly process.
  6. Chung Henry Wei-Ming (Cupertino CA), Interconnect structures for integrated circuits.
  7. Akram,Salman, Metallization structures for semiconductor device interconnects, methods for making same, and semiconductor devices including same.
  8. Yen Yung-Chau (San Jose CA), Metallization technique for integrated circuit structures.
  9. Liou Fu-Tai (Carrollton TX) Miller Robert O. (The Colony TX) Farohani Mohammed M. (Carrollton TX) Han Yu-Pin (Dallas TX), Method for forming a contact VIA.
  10. Roberts Martin C. ; Tang Sanh D., Method for forming an integrated circuit interconnect using a dual poly process.
  11. Roberts, Martin C.; Tang, Sanh D., Method for forming an integrated circuit interconnect using a dual poly process.
  12. Roberts, Martin C.; Tang, Sanh D., Method for forming an integrated circuit interconnect using a dual poly process.
  13. Jun Young Kwon,KRX, Method for forming multilayered interconnection of semiconductor device.
  14. Teo Yeow Meng,SGX, Method for forming stacked polysilicon.
  15. Choi Yang Kyu,KRX, Method for forming wiring of semiconductor device.
  16. Kurosawa Kei (Tokyo JPX), Method for manufacturing an electrical connection between conductor levels.
  17. Okamoto Tatsuo (Itami JPX) Kotani Hideo (Itami JPX) Oono Takio (Itami JPX) Watabe Kiyoto (Itami JPX) Kinoshita Yasushi (Itami JPX) Nishikawa Yoshikazu (Itami JPX), Method for manufacturing interconnection structure in semiconductor device.
  18. Rhodes, Howard E.; Tran, Luan, Method of making a semiconductor device having improved contacts.
  19. Ueda Seiji (Ohtsu City JPX), Method of making interconnects between polysilicon layers.
  20. Taka Shin-ichi (Kawasaki JPX) Ohshima Jiro (Kawasaki JPX) Abe Masahiro (Yokohama JPX) Aoyama Masaharu (Fujisawa JPX), Method of manufacturing a semiconductor device with conductive trench sidewalls.
  21. Tsuboi Atsushi,JPX, Method of manufacturing semiconductor device having multilevel interconnection.
  22. James Brady ; Tsiu Chiu Chan ; David Scott Culver, Methods for fabricating memory cells and load elements.
  23. Akram, Salman, Methods for making metallization structures for semiconductor device interconnects.
  24. Akram, Salman, Methods for making metallization structures for semiconductor device interconnects.
  25. Givens, John H.; Jost, Mark E., Methods for utilization of disappearing silicon hard mask for fabrication of semiconductor structures.
  26. Matsuda Tetsuo (Kunitachi JPX), Multilayer wiring technique for a semiconductor device.
  27. Chan Tsiu Chiu ; Bryant Frank Randolph, SRAM cell structure with dielectric sidewall spacers and drain and channel regions defined along sidewall spacers.
  28. Chan Tsiu Chiu ; Bishop William A., Semiconductor device with resistive load element.
  29. Givens, John H.; Jost, Mark E., Utilization of disappearing silicon hard mask for fabrication of semiconductor structures.
  30. Givens, John H.; Jost, Mark E., Utilization of disappearing silicon hard mask for fabrication of semiconductor structures.
  31. Rivoli Anthony L. (Palm Bay FL) Young William R. (Palm Bay FL), Vertical contact structure.
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