초록 ▼

An apparatus and a method for character and graphics pattern generation in a bit mapped graphics display system is disclosed that includes a pixel data manager 14 for supplying character bit maps and graphics patterns to a visible display memory 22. A character information memory 24 is utilized for

An apparatus and a method for character and graphics pattern generation in a bit mapped graphics display system is disclosed that includes a pixel data manager 14 for supplying character bit maps and graphics patterns to a visible display memory 22. A character information memory 24 is utilized for the storage of character descriptive information which includes an address table 26, macro-instructions 28, 30, and 32, and character bit maps 34, 36, and 38. Each character in a set of characters has an associated macro-instruction and character bit map. The address table contains memory addresses that point to the macro-instructions. Each macro-instruction contains executable instructions that establish the size and location of a corresponding character bit map. To supply a character to the visible display memory, the pixel data manager fetches and executes a corresponding macro-instruction. Overhead burden on the central processing unit is minimized.

대표청구항 ▼

In an apparatus having a character information memory and a visible display memory, wherein said character information memory includes descriptive information for a character set, said descriptive information includes an address table, pairs of macro-instructions and character bit maps, each of said

In an apparatus having a character information memory and a visible display memory, wherein said character information memory includes descriptive information for a character set, said descriptive information includes an address table, pairs of macro-instructions and character bit maps, each of said pairs of macro-instructions corresponds to one character of said character set, at least one of said macro-instructions in each of said pairs includes a character address that points to the memory location of its corresponding character bit map, and said address table includes macro-instruction addresses that point to the memory locations of said macro-instructions, said apparatus comprising: processing means coupled to said character information memory and to said visible display memory for fetching a designated portion of the contents of said display memory and a character code that designates a character in said character information memory which is to be combined with said designated portion of the contents of said display memory, said processing means including means for fetching said pair of macro-instructions which correspond to said character code from said character information memory, and means including an arithmetic logic unit means for executing said pair of macro-instructions to selectively combine logically or arithmetically said character from said character information memory with said designated portion of said contents of said visible display memory and copy the result therefrom back into said visible display memory.