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Self configuring bus structure for computer network 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/00
  • G06F-013/40
출원번호 US-0558778 (1983-12-06)
발명자 / 주소
  • Ceccon Claude R. (Tucson AZ) Mioduski Paul C. (Tucson AZ)
출원인 / 주소
  • Tri Sigma Corporation (Scottsdale AZ 02)
인용정보 피인용 횟수 : 27  인용 특허 : 9

초록

A computer bus structure includes a plurality of separate bus segments on a mother board. Plugging in of each of a plurality of interface boards automatically connects the right-hand portion of a particular bus segment to the left-hand portion of an adjacent bus segment so that a local bus of the ne

대표청구항

A reconfigurable bus structure in a system including a first processor and a first group of interface circuits for connection to said first processor, said first processor and each of said interface circuits each being in electrical communication with a plurality of edge connector conductors, said r

이 특허에 인용된 특허 (9)

  1. Cohen Albert E. (Merrick NY) Hance William G. (Selden NY) Moir Ian (Stony Brook NY) Lane Thao (Rennes FRX) Caussarieu Frederic (Rennes FRX), Advanced network processor.
  2. Struger Odo J. (Chagrin Falls OH) Bremenour Edwin L. (Euclid OH) Burns James F. (Chagrin Falls OH) Jerva Ronald E. (Mentor-on-the-Lake OH), Circuit board assembly with disconnect arm.
  3. Neumann Leopold (Lexington MA) Shapiro Gerald N. (Newton MA) Mattedi Bruno A. (Andover MA), Command bus.
  4. Kober Rudolf (Munich DEX), Data exchange processor for distributed computing system.
  5. Bunnell Edward D. (Palm Harbor FL), High density mother/daughter circuit board connector.
  6. Grinberg Jan (Los Angeles CA) Hansen Siegfried (Los Angeles CA), Modular input-programmable logic circuits for use in a modular array processor.
  7. Finch Larry R. (Newark Valley NY) Roche Joseph D. (Endicott NY) Rogers Paul M. (Apalachin NY), Planar board and card-on-board electronic package assembly.
  8. McVey James M. (Leander TX), Programmable I/O device identification.
  9. Gonzales Roman Y. (Andover MA), Universal input/output system construction for programmable controllers.

이 특허를 인용한 특허 (27)

  1. Spisak, Kevin C.; Hagen, Michael S., Apparatus for data bus expansion between two instrument chassis.
  2. Schoellkopf Jean-Pierre (Grenoble FRX) Boyer-Chammard Yann (Boulogne-Billancourt FRX), Bus control device comprising a plurality of isolatable segments.
  3. Kirk John (Boxboro MA) Narhi Larry (Bolton MA), Bus data path control scheme.
  4. Wooten David R. (Spring TX), Cached subtractive decode addressing on a computer bus.
  5. Toms John Shackelford ; Brown Steven M. ; Miller William L. ; Weller George V. ; Russell Scott H. ; Branc Joseph R. ; Sweeton David C. ; Mikolajczak Matthew M., Communications network for identifying the location of articles relative to a floor plan.
  6. Toms John Shackelford ; Brown Steven M. ; Miller William L. ; Weller George V. ; Russell Scott H. ; Branc Joseph R. ; Sweeton David C. ; Mikolajczak Matthew M., Communications network for identifying the location of articles relative to a floor plan.
  7. Farmwald,Michael; Horowitz,Mark, Controller device and method for operating same.
  8. John Shackelford Toms ; Steven M. Brown ; William L. Miller ; George V. Weller ; Scott H. Russell ; Joseph R. Branc ; David C. Sweeton ; Matthew M. Mikolajczak, Furniture unit having a modular communication network.
  9. Toms John Shackelford ; Brown Steven M. ; Miller William L. ; Weller George V. ; Russell Scott H. ; Branc Joseph R. ; Sweeton David C. ; Mikolajczak Matthew M., Furniture unit having a modular communication network.
  10. Toms John Shackelford ; Brown Steven M. ; Miller William L. ; Weller George V. ; Russell Scott H. ; Branc Joseph R. ; Sweeton David C. ; Mikolajczak Matthew M., Furniture unit having a modular communication network.
  11. Farmwald Michael (Berkeley CA) Horowitz Mark (Palo Alto CA), Integrated circuit I/O using a high performance bus interface.
  12. Farmwald Michael ; Horowitz Mark, Integrated circuit I/O using a high performance bus interface.
  13. Annapareddy Narasimhareddy L. (San Jose CA) Finney Damon W. (San Jose CA) Jenkins Michael O. (San Jose CA) Kessler Larry B. (San Jose CA) Lang Donald J. (Cupertino CA) Liang Song C. (San Jose CA) Mor, Interconnection network for a multi-nodal data processing system which exhibits incremental scalability.
  14. Tuchler Daniel S. (Newton MA) Allen Bruce S. (Concord MA), Interrupt system for transmitting interrupt request signal and interrupt vector based upon output of synchronized counte.
  15. Farmwald Michael ; Horowitz Mark, Memory module having memory devices containing internal device ID registers and method of initializing same.
  16. Farmwald Michael ; Horowitz Mark, Method and apparatus for externally configuring and modifying the transaction request response characteristics of a sem.
  17. Yonekura Mikio (Hachioji JPX) Kinoshita Jiro (Yamato JPX), Method of allocating board slot numbers with altering software.
  18. Toms John Schackelford (University Heights OH) Brown Steven M. (Grand Rapids MI) Miller William L. (Ada MI) Weller George V. (Grand Rapids MI) Russell Scott H. (Kalamazoo MI) Branc Joseph R. (Grand R, Method of configuring a furniture utility distribution system.
  19. Farmwald Michael ; Horowitz Mark, Method of operating a memory device having a variable data output length and an identification register.
  20. Ludwig Thomas E. (Irvine CA) Craft Thomas W. (Mission Viejo CA), Microcomputer architecture utilizing an asynchronous bus between microprocessor and industry standard synchronous bus.
  21. Haapala, Kari; Kuosmanen, Kari; Mikkola, Lauri; Rissanen, Olli, Procedure for the configuration of a bus-type data transmission network.
  22. Taska John L. (Naperville IL), Radiation-coupled daisy chain.
  23. Hayes Dennis F. (Westford MA), Reconfigurable bus.
  24. Hayashi Kenichi (Kawasaki JPX) Chuang Isaac Liu (Prospect KY), Reconfigurable torus network having switches between all adjacent processor elements for statically or dynamically split.
  25. Craft Thomas W. (El Toro CA) Herrin Bradley T. (El Toro CA) Ludwig Thomas E. (Irvine CA), Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers.
  26. Farmwald Michael ; Horowitz Mark, Synchronous memory device having identification register.
  27. Gephardt Douglas D. ; Stewart Brett B. ; Wisor Rita M. ; Belt Steven L. ; Dutton Drew J., System for dynamically reconfiguring subbusses of data bus according to system needs based on monitoring each of the inf.
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