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A microprocessor device used as an adapter for a communications loop of the closed-ring, token-passing, local area network type. Each station on the ring has a host processor with a host CPU, a main memory, and a system bus. The microprocessor device, operating relatively independent of the host CPU

A microprocessor device used as an adapter for a communications loop of the closed-ring, token-passing, local area network type. Each station on the ring has a host processor with a host CPU, a main memory, and a system bus. The microprocessor device, operating relatively independent of the host CPU, is coupled to the main memory by the system bus and includes a local CPU, a local read/write memory, an on-chip timer, a local bus and a bus arbiter. A transmit/receive controller is connected between the ring and the microprocessor device. This controller is coupled to the local bus to directly access the local read/write memory, also under control of the bus arbiter. The local CPU executes instructions fetched from a ROM accessed by the local bus, so the local CPU instruction fetch, the direct memory access from the transmit/receive controller for transmitting or receiving data frames, and the access from the host CPU for copying transmitted or received message frames, all contend for the local bus. Bus arbitration with appropriate priorities is used to control access to the local bus. The on-chip timer accessed by the local bus provides the time period used to monitor and control the communications protocol.

대표청구항 ▼

A digital data communications system comprising: (a) a signal path, (b) a plurality of stations connected in said signal path, each station receiving digital data from the path and transmitting digital data to said path, each said station comprising: (i) a main processor containing a main CPU, a mai

A digital data communications system comprising: (a) a signal path, (b) a plurality of stations connected in said signal path, each station receiving digital data from the path and transmitting digital data to said path, each said station comprising: (i) a main processor containing a main CPU, a main memory, and peripheral I/O devices, and having a system bus interconnecting said CPU, main memory, and peripheral I/O devices; (ii) a single-chip microprocessor device containing a local CPU, a local read/write memory, local address/data bus means interconnecting said local CPU and local read/write memory, a timer having at least one count register accessed by said local bus means, and a bus arbiter coupled to and controlling access to said local bus means; said local CPU including an ALU, a plurality of registers, input/output port means, an instruction register, a control ROM having an input coupled to the instruction register, internal CPU bus means interconnecting inputs and outputs of the ALU with said registers and said input/output port means, and interrupt means for the local CPU; said input/output port means being coupled to said local bus means; (iii) coupling means connecting said system bus to said local bus means, sad main CPU accessing said local read/write memory and said local CPU accessing said main memory via said coupling means, (iv) receiving means having an input coupled to said signal path and an output coupled to said local bus means, and transmitting means having an output coupled to said signal path and an input coupled to said local bus means, (v) transmit/receive control means responsive to receipt of data from said signal path in said receiving means to directly access said local read/write memory via said local bus means for writing received data to the local read/write memory and reading transmit data from the local read/write memory via said local bus means.