초록 ▼

A digital TV system includes a CCU that is interconnected by a three-wire, high speed bus to a plurality of TV signal function modules for controlling operation thereof by means of a high speed hardware generated clock signal. A software generated clock signal in the CCU is supplied on a low speed t

A digital TV system includes a CCU that is interconnected by a three-wire, high speed bus to a plurality of TV signal function modules for controlling operation thereof by means of a high speed hardware generated clock signal. A software generated clock signal in the CCU is supplied on a low speed two-wire auxiliary device bus which is connected to microprocessors in a plurality of auxiliary devices for performing functions ancillary to TV signal processing. The microprocessor in each auxiliary device is an off-the-shelf type that does not require any special hardware because the timing on the auxiliary device bus is sufficiently slow to enable software monitoring of the line and data transfer.

대표청구항 ▼

A digital television system comprising: a high speed microprocessor controller including means for producing a high speed hardware generated clock signal and means for producing a low speed software generated clock signal; a plurality of television function modules for performing a plurality of tele

A digital television system comprising: a high speed microprocessor controller including means for producing a high speed hardware generated clock signal and means for producing a low speed software generated clock signal; a plurality of television function modules for performing a plurality of television signal processing functions; a plurality of auxiliary devices for performing functions ancillary to said television signal processing, each of said auxiliary devices including a standard off-the-shelf microprocessor including means for responding to software generated clock signals; a high speed communication bus linking said microprocessor controller and the high speed hardware generated clock signal with said plurality of television function modules for enabling control of the operation of said modules; a low speed communication link interconnecting said microprocessor controller and the low speed software generated clock signal with each of said microprocessors in said auxiliary devices; and the microprocessor in each of said auxiliary devices being in a slave relationship to said microprocessor controller and performing as data communication devices.