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Interface circuit having a shift register inserted between a data transmission unit and a data reception unit

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-003/00
  • G06F-005/00
출원번호 US-0514902 (1983-07-18)
우선권정보 JP-0123876 (1982-07-16)
발명자 / 주소
  • Nukiyama Tomoji (Tokyo JPX)
출원인 / 주소
  • NEC Corporation (Tokyo JPX 03)
인용정보 피인용 횟수 : 36  인용 특허 : 4

초록

An interface unit for connecting a transmitting unit to a receiving unit, the transmitting being capable of transmitting data at a speed greater than the processing speed of the receiving unit. The interface includes a serially connected multistage register which receives input data from the transmi

대표청구항

An interface circuit inserted between a data transmission unit and a data reception unit comprising a shift register having a plurality of serially coupled register stages, each register stage having a data input gate, a data storage means for storing data applied thereto through the data input gate

이 특허에 인용된 특허 (4)

  1. Clark Becky J. (La Jolla CA) Seitz Charles L. (Palo Alto CA), Asynchronous self timed queue.
  2. Hargrove Arthur K. (Irvine CA) Brown Ronald L. (Fountain Valley CA), FIFO Register with independent clocking means.
  3. Berglund Neil C. (Kasson MN) Nieling James R. (Rochester MN), Maintenance interface for a service processor-central processing unit computer system.
  4. Lunsford ; John Albert ; Martinson ; Lloyd William, Output buffer synchronizing circuit having selectively variable delay means.

이 특허를 인용한 특허 (36)

  1. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  2. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  3. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  4. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  7. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  8. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  9. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  10. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  11. Akashi Mineo (Tokyo JPX), Data input circuit having latch circuit.
  12. Toda Haruki,JPX, Data transfer system for transferring data in synchronization with system clock and synchronous semiconductor memory.
  13. Tamura Toshiyuki (Itami JPX) Komori Shinji (Itami JPX) Takata Hidehiro (Itami JPX) Yamasaki Tetsuo (Amagasaki JPX) Terada Hiroaki (Suita JPX) Asada Katsuhiko (Amagasaki JPX), Data transmission apparatus with loopback topology.
  14. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  15. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  16. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  17. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  18. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  19. Giacobbe Paul J. ; Ryan Robert P., Frequency independent asynchronous clock crossing FIFO.
  20. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  21. Ramchandran,Amit, Input pipeline registers for a node in an adaptive computing engine.
  22. Suzuki Takashi (Hamamatsu JPX), Interface circuit for asychronous data transfer.
  23. Stuart-Bruges William P. (Cholderton ; Nr. Salisbury GBX), Method and apparatus for transmitting and processing data from well logging tool.
  24. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  25. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  26. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  27. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  28. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  29. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  30. Nuechterlein David W. (Durham NC) Rinaldi Mark A. (Durham NC), Parallel pipelined processor.
  31. Iwamura Masahiro,JPX ; Tanaka Shigeya,JPX ; Hotta Takashi,JPX ; Yamauchi Tatsumi,JPX ; Mori Kazutaka,JPX, Pipelined semiconductor devices suitable for ultra large scale integration.
  32. Masahiro Iwamura JP; Shigeya Tanaka JP; Takashi Hotta JP; Tatsumi Yamauchi JP; Kazutaka Mori JP, Pipelined semiconductor devices suitable for ultra large scale integration.
  33. Sakata Toshikazu,JPX, Register device.
  34. Bentley Steven R. (Tucson AZ) Fickle David M. (Tucson AZ) Nylander-Hill Pamela R. (Tucson AZ), System for efficiently transferring data between a high speed channel and a low speed I/O device.
  35. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
  36. Sano,Kazuaki, Use of and gates with a write control circuit for trimming a bleeder resistor.
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