초록 ▼

Circuitry for automatically configuring the operating system software of a computer is disclosed. The circuitry includes a revision port which generates a unique eight-bit code indicating the latest revision level of the main circuit board in the computer. Each time revisions are made in the board d

Circuitry for automatically configuring the operating system software of a computer is disclosed. The circuitry includes a revision port which generates a unique eight-bit code indicating the latest revision level of the main circuit board in the computer. Each time revisions are made in the board during manufacturing or each time a circuit board containing new revisions is put into the system by maintenance or service personnel, the eight-bit code generated by the port is changed. During the process of configuring the operating system software, the central processing unit reads the code generated by the port and uses the revision information to load and link software routines which will operate properly with the revised circuitry.

대표청구항 ▼

A computer system comprising, a central processing unit having a control bus for transferring control signals between said central processing unit and various peripheral units and a data bus for transferring data between said central processing unit and the remainder of the computer system, said cen

A computer system comprising, a central processing unit having a control bus for transferring control signals between said central processing unit and various peripheral units and a data bus for transferring data between said central processing unit and the remainder of the computer system, said central processing unit being comprised of a plurality of circuit modules subject to circuit revisions and means for assembling operating systems software; a programmable interface unit, said interface unit having a plurality of ports and being controlled by control signals on said control bus for transferring information between one of said ports and said data bus and for generating interface control signals at another of said ports when said central processing unit is assembling the operating system software; a control decoder responsive to said interface control signals for generating an enable control signal, a buffer circuit having a plurality of inputs and a plurality of outputs, said outputs being connected via said one of said ports of said programmable interface unit to said data bus in response to said enable control signal; and means for generating at said inputs of said buffer circuit a code number corresponding to the revision level of said circuit modules; said central processing unit including means for reading, during assembling of the operating system software, said code number from said data bus and for using said revision level information in said code number to load and link software routines which will operate properly with the revised circuit modules.