초록 ▼

A microprogrammed data processor in which the average processing speed is significantly enhanced by very rapidly processing system-initiated control operations using multiplexed programmable logic arrays. A wide input system encoding programmable logic array (270) responds to input signals which ins

A microprogrammed data processor in which the average processing speed is significantly enhanced by very rapidly processing system-initiated control operations using multiplexed programmable logic arrays. A wide input system encoding programmable logic array (270) responds to input signals which instruct system-initiated control operations, such as interrupts, power failure shut-down operations, system reset operations, ets., to produce internal exception condition opcodes. These opcodes are applied to inputs of a plurality of system decode programmable logic arrays (251-254) which, in response to the opcodes, generate sequences of microwords for executing the system-initiated control operations. The system decode programmable logic arrays (251-254) are activated sequentially and cyclically to generate the sequences of microwords used to carry out each of the control operations. The outputs of the system decode programmable logic arrays are multiplexed onto two data buses (214, 218), and the microwords on the two data buses (214, 218) are alternately decoded to produce control point signals used to directly control the operations of internal processor operational elements such as the arithmetic logic unit, registers, counters and the like.

대표청구항 ▼

In a microprogrammed data processor wherein sequences of microwords are used to control the execution of processor instructions, some of said microwords being produced in response to software-initiated control instructions during a run mode of said data processor and others of said microwords being

In a microprogrammed data processor wherein sequences of microwords are used to control the execution of processor instructions, some of said microwords being produced in response to software-initiated control instructions during a run mode of said data processor and others of said microwords being produced in response to hardware-initiated control instructions in a non-run mode of said data processor, an improved microword control system comprising: a first plurality of programmable logic array mechanisms responsive to said hardware-initiated control instructions in a non-run mode of said data processor for producing first sequences of microwords for executing said instructions; microword-responsive control circuitry for controlling operations of predetermined hardware elements of said data processor in response to said first sequences of microwords; a second plurality of second programmable logic array mechanisms responsive to said software-initiated instructions in a run mode of said data processor for producing microwords for executing said software initiated instructions; clock generation means for generating a plurality of sequences of clock pulses; first multiplexing circuitry for supplying microwords from different ones of said first plurality of programmable logic array mechanisms to said control circuitry during respective ones of said clock pulse sequences; and second multiplexing circuitry for supplying microwords from different ones of said second plurality of programmable logic array mechanisms to said control circuitry during different respective time intervals.