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특허 상세정보

MyON담기
내보내기 페이스북 공유 카카오톡 공유

Two axis fast access memory

특허상세정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) G09G-001/16   
미국특허분류(USC) 340/747 ; 340/798 ; 340/727
출원번호 US-0505630 (1983-06-20)
발명자 / 주소
출원인 / 주소
인용정보 피인용 횟수 : 78  인용 특허 : 5
초록
▼

The disclosure relates generally to a computer generated synthesized imaging system. More particularly, the invention relates to a method and apparatus for providing fast access to a two axis memory wherein consecutive data elements in both row and column orientation of a data set represented as a matrix may be obtained at a rate faster than the access time of memory elements utilized. A speed-up of access speed by a factor N may be achieved, where N is a power of 2 (2, 4, 8, 16 . . . ). The memory elements are organized in N independently addressable ba...

대표
청구항
▼

A method for image address to memory address mapping comprising the steps of demultiplexingly mapping pixels of a two axis (A×A) square array image into 2N memory banks such that memory elements corresponding to any 2N consecutive pixels of any row and any column of said image reside in different banks and can be accessed simultaneously, said mapping yielding a stream of corresponding row or column oriented pixels with each pixel being identified by its image row and column positions, assigning a designated memory bank and an address therein to each of s...

이 특허에 인용된 특허 (5)

  1. Schtt Dieter (Munich DEX) Schwengler Manfred (Sindelfingen DEX) Ulland Hartmut (Stuttgart DEX) Weis Helmut H. (Waldenbuch DEX). Device for storing and displaying graphic information. USP1984044442503.
  2. Morrin Thomas Harvey (San Jose CA) Van Voorhis David Curtis (Los Gatos CA). Method and apparatus for accessing horizontal sequences, vertical sequences and regularly spaced rectangular subarrays f. USP1976123996559.
  3. Morrin ; II Thomas Harvey (San Jose CA) Van Voorhis David C. (Los Gatos CA). Method and apparatus for accessing horizontal sequences, vertical sequences, and rectangular subarrays from an array sto. USP1976113995253.
  4. Mossaides Paula X. (Canby OR). Method and apparatus for displaying images. USP1985044509043.
  5. Bennett, William S.. Methods and apparatus for blending computer image generated features. USP1983054384338.

이 특허를 인용한 특허 피인용횟수: 78

  1. Wiedemann, Melissa; Phurrough, Larry; Gratsch, Colleen Flynn; Skoblick, Richard; Lee, Harry C.. Automatic image object identification using threshold gradient magnitude based on terrain type. USP2012038135174.
  2. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd. Bus systems and reconfiguration methods. USP2012028127061.
  3. Vorbach, Martin; Münch, Robert. Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs. USP2010107822968.
  4. Vorbach, Martin; Nückel, Armin. Configurable logic integrated circuit having a multidimensional structure of configurable elements. USP2014058726250.
  5. Vorbach, Martin; Thomas, Alexander. Data processing device and method. USP2014088812820.
  6. Vorbach, Martin; Thomas, Alexander. Data processing device and method. USP2012038145881.
  7. Vorbach, Martin; Thomas, Alexander. Data processing device and method. USP2010117844796.
  8. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank. Data processing method and device. USP2014128914590.
  9. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank. Data processing method and device. USP2012048156284.
  10. Vorbach, Martin; Münch, Robert. Data processor having disabled cores. USP2014088819505.
  11. Hempel Bruce C. (Tivoli NY) Liang Bob C. (West Hurley NY). Data transformation and clipping in a graphics display system. USP1989044821209.
  12. Vorbach, Martin. Device including a field having function cells and information providing cells controlled by the function cells. USP2013048429385.
  13. Girard,Martin. Generating image data. USP2006117142709.
  14. Beaven Paul A. (Romsey GBX) Hawes Adrian J. (Chandlers Ford GBX) Llewelyn Roger J. (Winchester GBX). Graphic display apparatus with combined bit buffer and character graphics store. USP1990034910505.
  15. Fredrickson Robert W. (Ft. Collins CO) Shah Monish S. (Ft. Collins CO). Graphics frame buffer with pixel serializing group rotator. USP1990094958302.
  16. Vorbach, Martin; May, Frank. Hardware definition method including determining whether to implement a function as hardware or software. USP2012088250503.
  17. Pinkus, Alan R.; Parisi, Vincent M.. Helicopter brown-out landing. USP2010017642929.
  18. Narendra Patrenahalli M. (Edina MN) Fant Karl M. (Minneapolis MN) Graf Carl P. (Forest Lake MN). Human engineered remote driving system. USP1989084855822.
  19. Vorbach, Martin; Münch, Robert. I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures. USP2010017650448.
  20. Vorbach, Martin; Münch, Robert. I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures. USP2012068195856.
  21. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens. Logic cell array and bus system. USP2009097595659.
  22. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens. Logic cell array and bus system. USP2013068471593.
  23. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens. Logic cell array and bus system. USP2011118058899.
  24. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens. Logical cell array and bus system. USP2015069047440.
  25. Hirano Motoki,JPX ; Harada Kaoru,JPX. Map display apparatus. USP1999105964810.
  26. Wiedemann, Melissa; Phurrough, Larry; Gratsch, Colleen Flynn; Skoblick, Richard; Lee, Harry C.. Method and apparatus for automatic identification of linear objects in an image. USP2010037672484.
  27. Wiedemann, Melissa; Phurrough, Larry; Gratsch, Colleen Flynn; Skoblick, Richard; Lee, Harry C.. Method and apparatus for automatic identification of objects in an image. USP2010037676065.
  28. Wiedemann, Melissa; Phurrough, Larry; Gratsch, Colleen Flynn; Skoblick, Richard; Lee, Harry C.. Method and apparatus for automatic linear object identification using identified terrain types in images. USP2011027894675.
  29. Wiedemann, Melissa; Phurrough, Larry; Gratsch, Colleen Flynn; Skoblick, Richard; Lee, Harry C.. Method and apparatus for automatic object identification. USP2011077983446.
  30. Vorbach, Martin; May, Frank; Nuckel, Armin. Method and device for processing data. USP2010027657861.
  31. Vorbach, Martin; May, Frank; Nuckel, Armin. Method and device for processing data. USP2012108281265.
  32. Ollmann, Ian R.. Method and system for fast 90 degree rotation of arrays. USP2010087768531.
  33. Ollmann,Ian R.. Method and system for fast 90 degree rotation of arrays. USP2009037511722.
  34. Vorbach, Martin. Method for debugging reconfigurable architectures. USP2013038407525.
  35. Vorbach, Martin. Method for debugging reconfigurable architectures. USP2011118069373.
  36. Vorbach, Martin; May, Frank; Nückel, Armin. Method for debugging reconfigurable architectures. USP2010117840842.
  37. Vorbach, Martin; Nückel, Armin. Method for interleaving a program over a plurality of cells. USP2012078230411.
  38. Ritter, Dieter. Method for obtaining a three-dimensional map representation, and a navigation system. USP2003096628278.
  39. Vorbach, Martin; Nückel, Armin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva. Method for processing data. USP2010027657877.
  40. Vorbach, Martin; May, Frank; Nückel, Armin. Method for the translation of programs for reconfigurable architectures. USP2014108869121.
  41. Mouchot Carine (Conflans Ste Honorine FRX) Frappier Grard (Paris FRX). Method of representing a perspective image of a terrain and a system for implementing same. USP1990074940972.
  42. Vorbach, Martin; Munch, Robert M.. Method of self-synchronization of configurable elements of a programmable module. USP201409RE45109.
  43. Vorbach, Martin; Münch, Robert M.. Method of self-synchronization of configurable elements of a programmable module. USP201410RE45223.
  44. Vorbach, Martin; Münch, Robert M.. Method of self-synchronization of configurable elements of a programmable module. USP201307RE44365.
  45. Vorbach, Martin; Baumgarte, Volker. Methods and devices for treating and processing data. USP2015079075605.
  46. Vorbach, Martin; Baumgarte, Volker. Methods and devices for treating and processing data. USP2012018099618.
  47. Vorbach, Martin; Baumgarte, Volker. Methods and devices for treating and processing data. USP2012118312301.
  48. Vorbach, Martin. Methods and devices for treating and/or processing data. USP2009087581076.
  49. Taniguchi, Toshinori; Tagawa, Norio; Matsuda, Makoto. Moving picture data compression device. USP2004056731809.
  50. Yule Raymond C. (La Habra Heights CA). Multiple disk memory access arrangement for gridded type data. USP1989074847807.
  51. Vorbach, Martin. Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization. USP2009087577822.
  52. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin. Pipeline configuration protocol and configuration unit communication. USP2012108301872.
  53. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin. Pipeline configuration protocol and configuration unit communication. USP2013068468329.
  54. Vorbach, Martin; Münch, Robert. Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like). USP2010107822881.
  55. Vorbach, Martin. Processor arrangement on a chip including data processing, memory, and interface elements. USP2015059037807.
  56. Vorbach, Martin; Münch, Robert. Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units. USP2012048156312.
  57. Vorbach, Martin; Nückel, Armin. Processor chip including a plurality of cache elements connected to a plurality of processor cores. USP2012118312200.
  58. Duthuit Olivier (Paris FRX) Bonnet Thierry (Champigny FRX) Martin Philippe (Fresnes FRX). Processor for the elimination of concealed faces for the synthesis of images in three dimensions. USP1989034812988.
  59. Vorbach, Martin. Reconfigurable elements. USP2014048686475.
  60. Vorbach, Martin. Reconfigurable elements. USP2014048686549.
  61. Vorbach, Martin; Baumgarte, Volker. Reconfigurable general purpose processor having time restricted configurations. USP2012108281108.
  62. Vorbach, Martin. Reconfigurable sequencer structure. USP2009107602214.
  63. Vorbach, Martin. Reconfigurable sequencer structure. USP2014088803552.
  64. Vorbach, Martin. Reconfigurable sequencer structure. USP2012118310274.
  65. Vorbach, Martin. Reconfigurable sequencer structure. USP2010087782087.
  66. Willis Donald Henry. Reduction of visibility of spurious signals in video. USP1999115982453.
  67. Vorbach, Martin; Bretz, Daniel. Router. USP2012068209653.
  68. Vorbach, Martin; Münch, Robert. Runtime configurable arithmetic and logic cell. USP2009077565525.
  69. Tanaka Shigeru (Fujisawa JPX). Semiconductor frame buffer memory. USP1989054833657.
  70. Alessandro Brigati IT; Jean Devin FR; Bruno Leconte FR. Set of two memories on the same monolithic integrated circuit. USP2002086434056.
  71. Brigati Alessandro,FRX ; Devin Jean,FRX ; Leconte Bruno,FRX. Set of two memories on the same monolithic integrated circuit. USP2001036205512.
  72. Brigati Alessandro,FRX ; Devin Jean,FRX ; Leconte Bruno,FRX. Set of two memories on the same monolithic integrated circuit. USP2001086279068.
  73. Brokenshire,Daniel Alan; Fossum,Gordon Clyde; Minor,Barry L. System and method for DMA controller with multi-dimensional line-walking functionality. USP2008047363397.
  74. Edgar Albert D. (Austin TX). System and method for image mapping in linear space. USP1997015598186.
  75. Brokenshire, Daniel Alan; Fossum, Gordon Clyde; Minor, Barry L. System and product for DMA controller with multi-dimensional line-walking functionality. USP2010047694036.
  76. Ando Hisashige (Yokohama JPX) Katsuyama Makoto (Kawasaki JPX) Sakuraba Takahiro (Kawasaki JPX). Vector pattern processing circuit for bit map display system. USP1989124888584.
  77. Perlman Stephen G. (Mountain View CA). Video display apparatus. USP1989094868557.
  78. Abraham Arthur (Oakland CA) Ellis ; Jr. George A. (San Francisco CA). Video signal receiver for computer graphics system. USP1988104777486.

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