$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Semiconductor chip interface 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/52
  • H01L-023/40
  • H01L-023/12
출원번호 US-0604783 (1984-04-27)
발명자 / 주소
  • Lee James C. K. (Los Altos CA) Amdahl Gene M. (Atherton CA) Beck Richard L. (Cupertino CA) Quinn Robert F. (Cupertino CA) Sochor Jerzy R. (San Jose CA)
출원인 / 주소
  • Trilogy Computer Development Partners, Ltd. (Cupertino CA 02)
인용정보 피인용 횟수 : 75  인용 특허 : 6

초록

A semiconductor chip module for a semiconductor chip having an exposed front face with a two dimensional array of contacts is disclosed. A connector plate is located proximate the front face of the chip. The connector plate has a plurality of apertures which correspond to and are aligned with the co

대표청구항

A semiconductor chip module comprising: a semiconductor chip having an exposed front face with a two-dimensional array of contacts thereon; a connector plate immediately proximate the front face of the chip having a plurality of apertures corresponding to and aligned with the contacts on the semicon

이 특허에 인용된 특허 (6)

  1. Lamp Richard W. (Mendham NJ), Electrical connector employing conductive rectilinear elements.
  2. Ciccio Joseph A. (Winchester MA) Thun Rudolf E. (Carlisle MA) Fardy Harry J. (Chelmsford MA), Integrated circuit device package interconnect means.
  3. Chance Dudley A. (Danbury CT) Kopcsay Gerard V. (Yorktown Heights NY), LSI Chip carrier with buried repairable capacitor with low inductance leads.
  4. Gilbert, Barry K.; Schwab, Daniel J., Leadless chip carrier apparatus providing an improved transmission line environment and improved heat dissipation.
  5. Buchoff Leonard S. (Bloomfield NJ) Kosiarski Joseph P. (Englishtown NJ) Dalamangas Chris A. (Union NJ), Method of making electrically conductive connector.
  6. Desai Kamalesh S. (Wappingers Falls NY) Eggerding Carl L. (Wappingers Falls NY) Ferrante John A. (Sherman CT) Ricci Raymond (Wappingers Falls NY) Urfer Ernest N. (Hopewell Junction NY), Process and structure for minimizing delamination in the fabrication of multi-layer ceramic substrate.

이 특허를 인용한 특허 (75)

  1. Mahulikar Deepak ; Hoffman Paul R. ; Braden Jeffrey S., Ball grid array electronic package.
  2. Ma, Qing; Lee, Jin; Mu, Chun; Vu, Quat; Li, Jian; Mosley, Larry, COF packaged semiconductor.
  3. Chang Sung Chul ; Khandros Igor Y. ; Smith William D., Chip-scale carrier for semiconductor devices including mounted spring contacts.
  4. Faraci Tony ; DiStefano Thomas H. ; Smith John W., Connecting multiple microelectronic elements with lead deformation.
  5. Tony Faraci ; Thomas H. Distefano ; John W. Smith, Connecting multiple microelectronic elements with lead deformation.
  6. Smith John W. ; DiStefano Thomas H., Connection components with rows of lead bond sections.
  7. Ishihara Shousaku (Chigasaki JPX) Yokono Hitoshi (Fujisawa JPX) Fujita Tsuyoshi (Yokohama JPX) Satoh Ryohei (Yokohama JPX) Wasai Kiyotaka (Yokohama JPX), Connector and semiconductor device packages employing the same.
  8. Leonard L. Mora ; Farshad Ghahghahi, Contact escape pattern.
  9. Khoury Theodore A. ; Frame James W., Contact structure having silicon finger contactors and total stack-up structure using same.
  10. Khandros,Igor Y., Contact structures and methods for making same.
  11. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., ELECTRICAL CONTACT STRUCTURES FORMED BY CONFIGURING A FLEXIBLE WIRE TO HAVE A SPRINGABLE SHAPE AND OVERCOATING THE WIRE WITH AT LEAST ONE LAYER OF A RESILIENT CONDUCTIVE MATERIAL, METHODS OF MOUNTING.
  12. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y; Mathieu, Gaetan L., ELECTRICAL CONTACT STRUCTURES FORMED BY CONFIGURING A FLEXIBLE WIRE TO HAVE A SPRINGABLE SHAPE AND OVERCOATING THE WIRE WITH AT LEAST ONE LAYER OF A RESILIENT CONDUCTIVE MATERIAL, METHODS OF MOUNTING.
  13. Khandros Igor Y., Electronic assembly comprising a substrate and a plurality of springable interconnection elements secured to terminals of the substrate.
  14. Eldridge Benjamin N. ; Khandros Igor Y. ; Mathieu Gaetan L. ; Pedersen David V., Electronic component with terminals and spring contact elements extending from areas which are remote from the terminals.
  15. Khandros Igor Y. ; Eldridge Benjamin N. ; Mathieu Gaetan L., Fabricating interconnects and tips using sacrificial substrates.
  16. DiStefano Thomas H. (Monte Sereno CA) Smith John W. (Palo Alto CA) Faraci Tony (Georgetown TX), Fan-out semiconductor chip assembly.
  17. DiStefano Thomas H. ; Smith John W. ; Faraci Tony, Fan-out semiconductor chip assembly.
  18. Distefano Thomas ; Smith John W. ; Faraci Anthony B., Fixtures and methods for lead bonding and deformation.
  19. Distefano Thomas ; Smith John W. ; Faraci Anthony B., Fixtures and methods for lead bonding and deformation.
  20. Smith John W. ; Haba Belgacem, Flexible lead structures and methods of making same.
  21. Smith, John W.; Haba, Belgacem, Flexible lead structures and methods of making same.
  22. Carey David H. (Austin TX), Flip substrate for chip mount.
  23. Carey David H. (Austin TX), Flip substrate for chip mount.
  24. Neugebauer Constantine A. (Schenectady NY) Daum Wolfgang (Schenectady NY), High current hermetic package including an internal foil and having a lead extending through the package lid and a packa.
  25. Masaaki Okada JP, High-density mounted device employing an adhesive sheet.
  26. Khandros Igor Y. ; Mathieu Gaetan L., Interconnection substrates with resilient contact structures on both sides.
  27. Dozier, II, Thomas H.; Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Interposer, socket and assembly for socketing an electronic component and method of making and using same.
  28. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Method and apparatus for burning-in semiconductor devices in wafer form.
  29. Haim Feigenbaum ; Chris M. Schreiber, Method for joining an integrated circuit.
  30. Khandros Igor Y., Method for manufacturing raised electrical contact pattern of controlled geometry.
  31. Khandros, Igor Y., Method for manufacturing raised electrical contact pattern of controlled geometry.
  32. Khandros, Igor Y., Method for manufacturing raised electrical contact pattern of controlled geometry.
  33. Val Christian,FRX ; Campenhout Yves Van,FRX ; Gilet Dominique,FRX, Method for the manufacturing of a semiconductor device which comprises at least one chip and corresponding device.
  34. Khandros Igor Y., Method of mounting free-standing resilient electrical contact structures to electronic components.
  35. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Method of wirebonding that utilizes a gas flow within a capillary from which a wire is played out.
  36. Dozier, II, Thomas H.; Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Methods of removably mounting electronic components to a circuit board, and sockets formed by the methods.
  37. Ebert, Thomas, Micro-scale cooling element.
  38. DiStefano Thomas H. ; Smith John W., Microelectronic assemblies with multiple leads.
  39. DiStefano Thomas H. ; Smith John W., Microelectronic assemblies with multiple leads.
  40. DiStefano, Thomas H.; Smith, John W., Microelectronic assemblies with multiple leads.
  41. Khandros,Igor Y.; DiStefano,Thomas H., Microelectronic component and assembly having leads with offset portions.
  42. Khandros,Igor Y.; DiStefano,Thomas H., Microelectronic component and assembly having leads with offset portions.
  43. Fjelstad Joseph, Microelectronic connector with planar elastomer sockets.
  44. Fjelstad, Joseph, Microelectronic connector with planar elastomer sockets.
  45. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Microelectronic contact structure.
  46. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Microelectronic contact structure and method of making same.
  47. Smith John W. ; Distefano Thomas H., Microelectronic element bonding with deformation of leads in rows.
  48. DiStefano Thomas H. ; Smith John W., Microelectronic mounting with multiple lead deformation and bonding.
  49. Distefano Thomas H. ; Smith ; Jr. John W., Microelectronics unit mounting with multiple lead bonding.
  50. Eldridge,Benjamin N.; Grube,Gary W.; Khandros,Igor Y.; Mathieu,Gaetan L., Mounting spring elements on semiconductor devices, and wafer-level testing methodology.
  51. Neugebauer Constantine A. (Schenectady NY) Levinson Lionel M. (Schenectady NY) Glascock ; II Homer H. (Scotia NY) Eichelberger Charles W. (Schenectady NY) Wojnarowski Robert J. (Ballston Lake NY) Car, Multi-chip interconnection package.
  52. John W. Smith ; Belgacem Haba, Multi-layer substrates and fabrication processes.
  53. Bhansali Ameet, Power-ground plane for a C4 flip-chip substrate.
  54. Brodsky, William Louis; Chan, Benson; Gaynes, Michael Anthony; Markovich, Voya Rista, Printed wiring board interposer sub-assembly.
  55. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Probe card assembly and kit, and methods of making same.
  56. Khandros,Igor Y.; Mathieu,Gaetan L., Probe for semiconductor devices.
  57. Khandros,Igor Y.; Mathieu,Gaetan L., Probe for semiconductor devices.
  58. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Resilient contact structures for interconnecting electronic devices.
  59. Eldridge,Benjamin Niles; Grube,Gary William; Khandros,Igor Yan; Mathieu,Gaetan L., Resilient contact structures formed and then attached to a substrate.
  60. Khandros,Igor Y.; DiStefano,Thomas H., Semiconductor chip assemblies, methods of making same and components for same.
  61. Irons Robert Charles,GBX ; Billett Kevin Robert,GBX ; Evans Michael John,GBX, Semiconductor chips encapsulated within a preformed sub-assembly.
  62. Sudo Toshio (Kawasaki JPX), Semiconductor integrated circuit device.
  63. DiStefano,Thomas H.; Smith,John W.; Faraci,Tony, Semiconductor package with heat sink.
  64. Hosomi,Eiichi, Semiconductor packaging apparatus.
  65. Terada Haruhiko (Chiryu JPX) Kawagoe Shigeyuki (Anjo JPX), Side window for motor vehicle.
  66. Dozier, II, Thomas H.; Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L.; Pedersen, David V.; Stadt, Michael A., Sockets for "springed" semiconductor devices.
  67. Dozier, II, Thomas H.; Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L.; Pederson, David V.; Stadt, Michael A., Sockets for "springed" semiconductor devices.
  68. Dozier, II,Thomas H.; Eldridge,Benjamin N.; Grube,Gary W.; Khandros,Igor Y.; Mathieu,Gaetan L.; Pedersen,David V.; Stadt,Michael A., Sockets for "springed" semiconductor devices.
  69. Dozier ; II Thomas H. ; Khandros Igor Y., Solder preforms.
  70. Noda Yuji,JPX, Structure and method for mounting an electronic part.
  71. Lee James C. K. (Los Altos Hills CA) Amdahl Gene M. (Atherton CA) Beck Richard (Cupertino CA) Lee Chune (San Francisco CA) Hu Edward (Sunnyvale CA), System for detachably mounting semiconductors on conductor substrate.
  72. Khandros, Igor Y.; Mathieu, Gaetan L., Tip structures.
  73. Ludden Michael J. (12 Casson Rd. Swindon ; Wiltshire GB2) Smith Nicholas J. G. (11 N. Meadow Rd. Cricklade ; Wiltshire SN6 6LT GB2) Gibney Paul J. (7 Hathersage Moor Liden ; Swindon ; Wiltshire SN3 6, Uses of uniaxially electrically conductive articles.
  74. Smith Nicholas J. G. (Cricklade GB2) Ludden Michael Joseph (Swindon GB2) Nyholm Peter (Swindon GB2) Gibney Paul James (Swindon GB2), Uses of uniaxially electrically conductive articles.
  75. Ho, Kwun-Yao; Kung, Moriss, Vertical routing structure.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로