초록 ▼

A digital computer system having a memory system organized into procedure and data objects, each having a unique identifier code and an access control list, for storing items of information and a processor for processing data in response to instructions. The instructions contain operation codes and

A digital computer system having a memory system organized into procedure and data objects, each having a unique identifier code and an access control list, for storing items of information and a processor for processing data in response to instructions. The instructions contain operation codes and names representing data. Each name corresponds to a name table entry in a name table which contains information from which the processor determines the location and the format for the data. The name table entry specifies a base address of one of a set thereof which change value only when a call or a return instruction is executed. A name interpretation system fetches a name table entry, calculates the base address and a displacement using the name table entry and the current architectural base address and adds the base address to the displacement to form the address of the data represented by the name.

대표청구항 ▼

A digital computer system comprising memory means for storing and providing data items, said memory means including means for organizing said memory means into objects in which said data items are located in said memory means, each of said objects being identified by an object identifier and access

A digital computer system comprising memory means for storing and providing data items, said memory means including means for organizing said memory means into objects in which said data items are located in said memory means, each of said objects being identified by an object identifier and access to said data items being limited to a set of subjects which identify entities for which said digital computer system may access said data items and being further limited for each subject of said set of subjects to a set of memory operations, and memory operation means responsive to memory operation specifiers for determining whether a subject can perform an operation specified by a memory operation specifier, said memory operation specifier including a logical address specifying an object identifier and a location in an object identified thereby, and a memory command specifying a memory operation, and a representation of a current subject for which said digital computer system is currently accessing one of said data items specified by said logical address for performing the memory operation specified by said memory command on the data item specified by said logical address when said current subject is one of the set of subjects having access to the object specified by said logical address and when said memory command specifies one of said memory operations which said current subject may perform on the data items belonging to the object specified by said logical address, and wherein said data items include instructions comprising operation codes specifying operations of said digital computer system, certain instructions each further including a name representing a data item to be used in the operation specified by said operation code, and a plurality of name table entries of data items in said memory means, each of said name table entries corresponding to a name value and containing a base specifier for deriving a base address from an architectural base address of a set thereof for the addresses associated with a current instruction of said certain instructions, and a displacement specifier for deriving a displacement value specifying a displacement from said base address, and processor means connected to said memory means for processing said data items and providing said memory operation specifier and a representation of said current subject to said memory means in response to said instructions, said processor means including instruction decoding means for decoding the operation code in a current instruction of said instructions, logical address generation means for providing said logical addresses and including name interpretation means responsive to a name for deriving a descriptor for a name table entry corresponding to said name using said name value, for using said descriptor to fetch said name table entry from said memory means, and for using said corresponding name table entry to derive a base address using the architectural base addresses as specified by said base specifier and derive a displacement as specified by said displacement specifier and thereupon to add said displacement to said base address to produce a resolved address of said represented data item and produce said resolved descriptor using said resolved address and next instruction address generation means for providing the logical address of a next current instruction, and control means responsive to said operation code decoding means and said logical address generation means for controlling the operation of said processor means and providing the representation of said current subject and said memory operation specifier including the logical address provided by said logical address generation means to said memory means.