초록 ▼

A bus interface for interfacing between a processor and a shared bus is disclosed. The bus interface allows the exchange of data in the form of packets between the bus and the processor. An interface control device exchanges control data with the shared bus (e.g. identification signals, polling sign

A bus interface for interfacing between a processor and a shared bus is disclosed. The bus interface allows the exchange of data in the form of packets between the bus and the processor. An interface control device exchanges control data with the shared bus (e.g. identification signals, polling signals, control signals) in order to regulate accesses of the interface circuit to the shared bus. State machines (e.g. a transmitter and a receiver) including data pipelines, are responsive to control signals from the interface control device for exchanging data between the shared bus and a data storage device. An access control device both controls the flow of data between the processor and the data storage device and regulates access to the data storage device between the processor and the state machines.

대표청구항 ▼

An interface circuit for interfacing between a shared bus and a processor, both for extracting information, in the form of packets, from said bus and for transmitting information, in the form of packets, to said bus, said interface circuit comprising: interface control means for receiving control in

An interface circuit for interfacing between a shared bus and a processor, both for extracting information, in the form of packets, from said bus and for transmitting information, in the form of packets, to said bus, said interface circuit comprising: interface control means for receiving control information from said shared bus and transmitting control information to said shared bus in order to regulate accesses of said interface circuit to said shared bus independently of said processor; receiver means, responsive to control signals from said interface control means, for receiving data from said shared bus and for routing said data to a temporary data storage means; transmitter means, responsive to control signals from said interface control means, for transmitting data from said temporary data storage means to said shared bus; and access control means both for controlling the flow of data between said processor and said temporary data storage means and for regulating access to said storage means between said processor and said interface circuit.