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Frame synchronization devices utilize a frame alignment word decoder connected to the outputs of a shift register which receives on its input the received data bit stream. It is clocked by a clock signal generated from a selection of periods of the data bit stream timing signal reproducing a periodi

Frame synchronization devices utilize a frame alignment word decoder connected to the outputs of a shift register which receives on its input the received data bit stream. It is clocked by a clock signal generated from a selection of periods of the data bit stream timing signal reproducing a periodic pattern. This pattern is formed by relative bit locations within the duration of a frame certain at least of which are distributed according to the distribution of the bits of an alignment word in a frame and which form groups of the same size regularly distributed over the duration of a frame. This clock signal is generated in the device by a divider which divides by 20 or by 21 which imposes on it a periodic phase skip by the value of one period of the data bit stream timing for as long as the alignment word is not recognized by the decoder. The shift register is implemented in two parallel parts clocked by versions of the clock signal with a relative phase shift between them, one of which parts updates the other part in parallel on each phase skip of the clock signal.

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A frame synchronization device in a binary data transmission system in which the data is transmitted in the form of an isochronous bit stream organized into frames each provided with an alignment word with bits distributed within the frame, said device comprising: timing means for obtaining a recove

A frame synchronization device in a binary data transmission system in which the data is transmitted in the form of an isochronous bit stream organized into frames each provided with an alignment word with bits distributed within the frame, said device comprising: timing means for obtaining a recovered timing from the data bit stream and for generating a clock signal from said recovered timing by selecting periods of said recovered timing signal which correspond to a periodic pattern of bit locations over the duration of a frame with at least some of said bit locations corresponding to the bits of the alignment word within a frame, said periodic pattern of bit locations comprising n groups of q bit locations (where n and q are integers) regularly distributed over the duration of a frame; phase shifting means responsive to a phase shifting instruction for selectively shifting the phase of said clock signal by an amount equal to at least one period of said recovered timing; a serial input parallel output shift register having at least as many stages as the number of data bit locations in said periodic pattern and which is clocked by said clock signal fed to it by the timing and phase shifting means, said shift register receving said data bit stream at its input; a parallel input alignment word decoder connected to the shift register outputs which correspond within a pattern to the locations of the bits of an alignment word; and phase shifting control means delivering said phase shifting instruction to said phase shifting means when said decoder has not recognized the alignment word in the data bits within said shift register during a minimum period of two consecutive alignment word durations.