$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Process of forming integrated circuits with contact pads in a standard array 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B44C-001/22
  • B29C-037/00
  • H01L-023/48
  • H01L-029/44
출원번호 US-0917040 (1986-10-09)
발명자 / 주소
  • Quinn
  • Daniel J. (Carrollton TX) Mulholland Wayne A. (Plano TX) Bond Robert H. (Carrollton TX) Olla Michael A. (Flower Mound TX) Cupples Jerry S. (Carrollton TX) Tsitovsky Ilya L. (Farmers Branch TX
출원인 / 주소
  • Thomson Components - Mostek Corp. (Carrollton TX 02)
인용정보 피인용 횟수 : 133  인용 특허 : 2

초록

An integrated circuit chip includes a top layer of dielectric penetrated by conductive vias connecting electrical contacts within the integrated circuit proper to a network of electrical leads disposed on top of the dielectric layer; the network of leads, in turn, being connected to an array of cont

대표청구항

A method of attaching electrical leads to an integrated circuit having a plurality of electrical devices connected in an electrical circuit by a network of electrical conduction paths to a first array of input/output contacts comprising the steps of: applying a layer of dielectric over said electric

이 특허에 인용된 특허 (2)

  1. Lucas Michael R. (Baltimore MD), Method for interconnecting close lead center integrated circuit packages to boards.
  2. Barber Larry J. (Sunnyvale CA), Testable tape for bonding leads to semiconductor die and process for manufacturing same.

이 특허를 인용한 특허 (133)

  1. Distefano Thomas H., Bonding lead structure with enhanced encapsulation.
  2. Distefano Thomas H., Bonding lead structure with enhanced encapsulation.
  3. Broderick James (2930 Point East Dr. ; Bld. E Apt. E 601 N. Miami Beach FL 33160) Schaul Malcolm (9 Jack La. Marlboro NJ 07746), Buying guide.
  4. McLellan, Neil; Wagenhoffer, Katherine; Lin, Geraldine Tsui Yee; Kirloskar, Mohan, Cavity-type integrated circuit package.
  5. Lee, Jin-Yuan; Lo, Hsin-Jung, Chip assembly with interconnection by metal bump.
  6. Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Li-Ren; Lo, Hsin-Jung, Chip package and method for fabricating the same.
  7. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip package with die and substrate.
  8. Lin, Mou-Shiung; Chou, Chiu-Ming, Chip structure.
  9. Lin, Mou-Shiung; Chou, Chiu-Ming, Chip structure.
  10. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang; Lo, Hsin-Jung, Chip structure.
  11. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  12. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  13. Lin, Mou-Shiung, Chip structure with a passive device and method for forming the same.
  14. Kuo, Nick; Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Chu-Fu, Chip structure with bumps and testing pads.
  15. Fan, Chun Ho; Tsang, Kwok Cheung, Electronic components such as thin array plastic packages and process for fabricating same.
  16. Fan,Chun Ho; Tsang,Kwok Cheung, Electronic components such as thin array plastic packages and process for fabricating same.
  17. Six, Jean Claude G., Electronic device comprising an integrated circuit.
  18. Fan Nelson,HKX ; McLellan Neil,HKX, Exposed die leadless plastic chip carrier.
  19. Khandros Igor Y. ; Eldridge Benjamin N. ; Mathieu Gaetan L., Fabricating interconnects and tips using sacrificial substrates.
  20. Igor Y. Khandros ; Thomas H. Distefano, Face-up semiconductor chip assemblies.
  21. Knotts Thomas A. (Menlo Park CA), Gigahertz rate integrated circuit package incorporating semiconductive MIS power-line substrate.
  22. Lin, Mou-Shiung, High performance IC chip having discrete decoupling capacitors attached to its IC surface.
  23. Lin, Mou-Shiung, High performance system-on-chip discrete components using post passivation process.
  24. Lin, Mou-Shiung, High performance system-on-chip discrete components using post passivation process.
  25. Lin, Mou-Shiung, High performance system-on-chip inductor using post passivation process.
  26. Lin, Mou-Shing, High performance system-on-chip using post passivation process.
  27. Lin, Mou-Shiung, High performance system-on-chip using post passivation process.
  28. Sedberry Donald C. (Gwynedd PA), High-density circuit and method of its manufacture.
  29. Sedberry Donald C. (Gwynedd PA), High-density circuit and method of its manufacture.
  30. Spaziani Stephen (Nashua NH) Vaccaro Kenneth (Acton MA) Waters William (Bedford MA), Infrared receiver wafer level probe testing.
  31. Lee, Jin-Yaun; Lin, Mou-Shiung; Huang, Ching-Cheng, Integrated chip package structure using ceramic substrate and method of manufacturing the same.
  32. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using organic substrate and method of manufacturing the same.
  33. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using silicon substrate and method of manufacturing the same.
  34. Lin, Mou-Shiung; Lee, Jin-Yuan, Integrated circuit and method for fabricating the same.
  35. Lin, Mou-Shiung; Lee, Jin-Yuan, Integrated circuit and method for fabricating the same.
  36. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  37. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  38. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  39. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  40. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  41. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  42. Kirloskar,Mohan; Wagenhoffer,Katherine; Higgins, III,Leo M., Integrated circuit package and method for fabricating same.
  43. Kirloskar,Mohan; Wagenhoffer,Katherine; Higgins, III,Leo M., Integrated circuit package and method for fabricating same.
  44. McLellan,Neil; Lin,Geraldine Tsui Yee; Fan,Chun Ho; Kirloskar,Mohan; Varga,Ed A., Integrated circuit package and process for fabricating the same.
  45. Lin, Geraldine Tsui Yee; de Munnik, Walter; Kwan, Kin Pui; Lau, Wing Him; Tsang, Kwok Cheung; Fan, Chun Ho; McLellan, Neil, Integrated circuit package having a plurality of spaced apart pad portions.
  46. McLellan,Neil; Lin,Geraldine Tsui Yee; Fan,Chun Ho; Kirloskar,Mohan; Varga,Ed A., Integrated circuit package with partially exposed contact pads and process for fabricating the same.
  47. Khandros Igor Y. ; Mathieu Gaetan L., Interconnection substrates with resilient contact structures on both sides.
  48. Kwan,Kin Pui; Lau,Wing Him; Tsang,Kwok Cheung; Fan,Chun Ho; McLellan,Neil, Leadless plastic chip carrier.
  49. Fan,Chun Ho; Lin,Tsui Yee; Lau,Ping Sheung, Leadless plastic chip carrier and method of fabricating same.
  50. Fan, Chun Ho; Kwan, Kin Pul; Wong, Hoi Chi; McLellan, Neil, Leadless plastic chip carrier with contact standoff.
  51. McLellan, Neil; Fan, Chun Ho; Tsang, Kwok Cheung; Kwan, Kin Pui; Lau, Wing Him, Leadless plastic chip carrier with etch back pad singulation.
  52. McLellan,Neil; Fan,Chun Ho; Tsang,Kwok Cheung; Kwan,Kin Pui; Lau,Wing Him, Leadless plastic chip carrier with etch back pad singulation.
  53. McLellan,Neil; Fan,Chun Ho; Tsang,Kwok Cheung; Kwan,Kin Pui; Lau,Wing Him, Leadless plastic chip carrier with etch back pad singulation.
  54. McLellan,Neil; Fan,Chun Ho; Tsang,Kwok Cheung; Kwan,Kin Pui; Lau,Wing Him, Leadless plastic chip carrier with etch back pad singulation.
  55. Fan, Chun Ho; Lin, Tsui Yee; Tsang, Kin Yan; McLellan, Neil, Leadless plastic chip carrier with partial etch die attach pad.
  56. Schoenfeld, Aaron; Ma, Manny K. F.; Kinsman, Larry D.; Brooks, J. Mike; Allen, Timothy J., Method and apparatus for coupling a semiconductor die to die terminals.
  57. Schoenfeld, Aaron; Ma, Manny K. F.; Kinsman, Larry D.; Brooks, J. Mike; Allen, Timothy J., Method and apparatus for coupling a semiconductor die to die terminals.
  58. Schoenfeld, Aaron; Ma, Manny K. F.; Kinsman, Larry D.; Brooks, J. Mike; Allen, Timothy J., Method and apparatus for coupling a semiconductor die to die terminals.
  59. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Method for fabricating chip package with die and substrate.
  60. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  61. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  62. Turner Timothy E. (Roanoke TX), Method of improving the corrosion resistance of aluminum contacts on semiconductors.
  63. Nelson Gregory H. (Gilbert AZ) Lebow Sanford (Westlake Village CA) Nogavich Eugene (Gilbert AZ), Method of manufacture interconnect device.
  64. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  65. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  66. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  67. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  68. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  69. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  70. Igor Y. Khandros ; Thomas H. Distefano, Methods of making semiconductor chip assemblies.
  71. Khandros Igor Y. ; Distefano Thomas H., Methods of making semiconductor chip assemblies.
  72. Pflughaupt,L. Elliott; Gibson,David; Kim,Young Gon; Mitchell,Craig S.; Zohni,Wael; Mohammed,Ilyas, Microelectronic assembly having array including passive elements and interconnects.
  73. Khandros,Igor Y.; DiStefano,Thomas H., Microelectronic component and assembly having leads with offset portions.
  74. Khandros,Igor Y.; DiStefano,Thomas H., Microelectronic component and assembly having leads with offset portions.
  75. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Microelectronic contact structure.
  76. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Microelectronic contact structure and method of making same.
  77. Lin, Mou-Shiung; Lee, Jin-Yuan, Non-cyanide gold electroplating for fine-line gold traces and gold pads.
  78. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
  79. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
  80. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  81. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  82. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  83. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  84. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  85. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  86. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chips.
  87. Lin, Mou-Shiung, Post passivation interconnection schemes on top of the IC chips.
  88. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  89. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  90. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection structures.
  91. Lin, Mou-Shiung; Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
  92. McLellan, Neil; Fan, Chun Ho; Kwan, Kin Pui; Lau, Wing Him, Process for fabricating a leadless plastic chip carrier.
  93. McLellan,Neil; Fan,Chun Ho; Kwan,Kin Pui; Lau,Wing Him, Process for fabricating a leadless plastic chip carrier.
  94. Fan,Chun Ho; McLellan,Neil; Lau,Wing Him; Tse,Emily Shui Ming, Process for fabricating an integrated circuit package.
  95. Lovoi Paul A. (Saratoga CA), Self supporting flat video display.
  96. Khandros Igor Y. (Peekskill NY) Distefano Thomas H. (Bronxville NY), Semiconductor chip assemblies, methods of making same and components for same.
  97. Khandros,Igor Y.; DiStefano,Thomas H., Semiconductor chip assemblies, methods of making same and components for same.
  98. Khandros,Igor Y.; Distefano,Thomas H., Semiconductor chip assemblies, methods of making same and components for same.
  99. Frankowsky, Gerd, Semiconductor chip configuration with a layer sequence with functional elements contacted by contact pads.
  100. Khandros Igor Y. ; Distefano Thomas H., Semiconductor chip package with center contacts.
  101. Lin, Mou-Shiung; Lee, Jin-Yuan, Semiconductor chip structure.
  102. Lin, Mou-Shiung; Yen, Huei-Mei; Lo, Hsin-Jung; Chou, Chiu-Ming; Chen, Ke-Hung, Semiconductor chip with a bonding pad having contact and test areas.
  103. Lee, Wen-Chieh; Lin, Mou-Shiung; Chou, Chien-Kang; Liu, Yi-Cheng; Chou, Chiu-Ming; Lee, Jin-Yuan, Semiconductor chip with coil element over passivation layer.
  104. Lee, Wen-Chieh; Lin, Mou-Shiung; Chou, Chien-Kang; Liu, Yi-Cheng; Chou, Chiu-Ming; Lee, Jin-Yuan, Semiconductor chip with coil element over passivation layer.
  105. Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Ching-San; Lin, Mou-Shiung, Semiconductor chip with passivation layer comprising metal interconnect and contact pads.
  106. Lin, Mou-Shiung; Lo, Hsin-Jung; Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Ching-San, Semiconductor chip with post-passivation scheme formed over passivation layer.
  107. Lin, Mou-Shiung; Lo, Hsin-Jung; Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Ching-San, Semiconductor chip with post-passivation scheme formed over passivation layer.
  108. Shiah,Chun, Semiconductor die structure featuring a triple pad organization.
  109. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Semiconductor package with interconnect layers.
  110. Dozier ; II Thomas H. ; Khandros Igor Y., Solder preforms.
  111. Igor Y. Khandros ; Thomas H. DiStefano, Stacked chip assembly.
  112. Pflughaupt, L. Elliott; Gibson, David; Kim, Young-Gon; Mitchell, Craig S., Stacked packages.
  113. Pflughaupt, L. Elliott; Gibson, David; Kim, Young-Gon; Mitchell, Craig S.; Zohni, Wael; Mohammed, Ilyas, Stacked packages.
  114. Eric A. Johnson ; John S. Kresge, Stress relieved ball grid array package.
  115. Lin, Mou-Shiung; Lei, Ming-Ta; Lin, Chuen-Jye, Structure and manufacturing method of a chip scale package.
  116. Chou, Chiu-Ming; Lin, Mou-Shiung, Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures.
  117. McLellan,Neil; Pedron,Serafin; Higgins, III,Leo M.; Tsang,Kwok Cheung; Kwan,Kin Pui, Thin array plastic package without die attach pad and process for fabricating the same.
  118. Kirloskar,Mohan; Fan,Chun Ho; Tsang,Kwok Cheung; Kwan,Kin Pui, Thin leadless plastic chip carrier.
  119. Kirloskar,Mohan; Fan,Chun Ho; Tsang,Kwok Cheung; Kwan,Kin Pui, Thin leadless plastic chip carrier.
  120. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  121. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  122. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  123. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  124. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  125. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  126. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  127. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  128. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  129. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  130. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
  131. Lin, Mou-Shiung; Wei, Gu-Yeon, Voltage regulator integrated with semiconductor chip.
  132. Baek,Seung Duk; Jang,Dong Hyeon; Kim,Gu Sung; Lee,Kang Wook; Chung,Jae Sik, Wafer-level electronic modules with integral connector contacts.
  133. Lin, Mou-Shiung, Wirebond over post passivation thick metal.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로