초록 ▼

A silicon wafer is provided which does not employ individually bonded leads between the IR sensitive elements and the input stages of multiplexers. The wafer is first coated with lead selenide in a first detector array area and is thereafter coated with lead sulfide within a second detector array ar

A silicon wafer is provided which does not employ individually bonded leads between the IR sensitive elements and the input stages of multiplexers. The wafer is first coated with lead selenide in a first detector array area and is thereafter coated with lead sulfide within a second detector array area. The described steps result in the direct chemical deposition of lead selenide and lead sulfide upon the silicon wafer to eliminate individual wire bonding, bumping, flip chiping, planar interconnecting methods of connecting detector array elements to silicon chip circuitry, e.g., multiplexers, to enable easy fabrication of very long arrays. The electrode structure employed, produces an increase in the electrical field gradient between the electrodes for a given volume of detector material, relative to conventional electrode configurations.

대표청구항 ▼

Method of making a PbS-PbSe IR detector array comprising the steps of: a. providing a silicon wafer having a first group of electrodes thereon defining a first IR detector array area and a second group of electrodes thereon defining a second IR detector array area; b. chemically depositing a layer o

Method of making a PbS-PbSe IR detector array comprising the steps of: a. providing a silicon wafer having a first group of electrodes thereon defining a first IR detector array area and a second group of electrodes thereon defining a second IR detector array area; b. chemically depositing a layer of PbSe over said first and second array areas by: b.1 preparing a first bath having a lead to selenium ion ratio of about 5:1; b.2 immersing said silicon wafer in said first bath for a period of about 60 minutes, the initial temperature of said bath upon immersion being about 25°C., the final temperature at the termination of said period being about 50°C; b.3 providing a second bath having the lead to selenium ion ratio of said first bath and additionally including an iodide ion having a lead to iodide ion ratio of about 100:1, and repeating step b.2 to deposit an additional coat of PbSe on said silicon wafer; c. sensitizing said PbSe layer deposited upon said silicon wafer by heating said wafer in air at a temperature of about 375°C. for a period of about 90 minutes; d. removing the deposited PbSe from major areas of said wafer except from said first detector array area; e. thereafter chemically depositing at least one layer of PbS upon said silicon wafer by providing a third bath having a lead, sulfide, and hydroxide ion therein, the ratio of lead to sulfide ion being between 1:1.25 and 1:6, and the ratio of lead to hydroxide ion being between 1:7 and 1:12; f. inserting said silicon wafer into said third bath for a period of between 60 minutes and 90 minutes while elevating the temperature of said bath between an initial temperature of between 10°C. and 14°C. upon immersion of said wafer therein and a final temperature of between 70°C. and 80°C. upon removal of said wafer; and g. removing the resulting PbS layer from major areas of said silicon wafer except for said second detector array area.