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Selective electroless plating of vias in VLSI devices 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • C23C-018/34
출원번호 US-0835355 (1986-03-03)
발명자 / 주소
  • Georgiou George E. (Gillette NJ) Poli Gary N. (High Bridge NJ)
출원인 / 주소
  • American Telephone and Telegraph Company, AT&T Bell Laboratories (Murray Hill NJ 02)
인용정보 피인용 횟수 : 39  인용 특허 : 4

초록

Selective electroless plating of cobalt or nickel is utilized to form conductive plugs in high-aspect-ratio vias in VLSI devices. Particularly good results are obtained when an active or catalytic film is formed on the via bottoms to serve as a plating base.

대표청구항

A selective electroless plating method of forming microminiature conductive plugs in high-aspect-ratio vias defined in a dielectric layer disposed on one main planar surface of a wafer in which integrated-circuit devices are to be fabricated, at least one of said vias having at the bottom thereof an

이 특허에 인용된 특허 (4)

  1. Hooper Robert C. (Houston TX) Harrover Alexander J. (Missouri City TX) VanHoy Michael J. (Stafford TX) Terry Charles E. (Houston TX), Low cost method for forming elevated metal bumps on integrated circuit bodies employing an aluminum/palladium metallizat.
  2. Feldstein Nathan (63 Hemlock Cir. Princeton NJ 08540), Method for rendering non-platable semiconductor substrates platable.
  3. Denning Richard (Springfield NJ) Spak Mark A. (Edison NJ) Polhemus Barry (Hampton NJ), Method of applying thin metal deposits to a substrate.
  4. Sirinyan, Kirkor; Merten, Rudolf; Wolf, Gerhard D.; Giesecke, Henning; Claussen, Uwe; Ebneth, Harold, Surface metallized semiconductors.

이 특허를 인용한 특허 (39)

  1. Yakobson,Eric; Hurtubise,Richard; Witt,Christian; Chen,Qingyun, Capping of metal interconnects in integrated circuit electronic devices.
  2. Yakobson,Eric; Hurtubise,Richard; Witt,Christian; Chen,Qingyun, Capping of metal interconnects in integrated circuit electronic devices.
  3. O'brien, Kevin; Akolkar, Rohan; Indukuri, Tejaswi; Fajardo, Arnel M., Dual metal interconnects for improved gap-fill, reliability, and reduced capacitance.
  4. Zitko Mark W., Electroless nickel cobalt phosphorous composition and plating process.
  5. Yu Allen S. ; Steffan Paul J., Electroless plated semiconductor vias and channels.
  6. Xiang Qi ; Pramanick Shekhar, Elevated salicide technology.
  7. Smith,Kim R., Foam cleaning and brightening composition comprising a sulfate/bisulfate salt mixture.
  8. Sinha, Nishant; Morgan, Paul A., High aspect ratio fill method and resulting structure.
  9. Sinha, Nishant; Morgan, Paul A., High aspect ratio fill method and resulting structure.
  10. Dubin Valery M., Method for filling high aspect ratio openings of an integrated circuit to minimize electromigration failure.
  11. Iwanaga Shoichi (Yokohama JPX) Fujiwara Akio (Fujisawa JPX) Sowa Takayoshi (Fujisawa JPX) Yokono Hitoshi (Fujisawa JPX), Method for forming conductor layers and method for fabricating multilayer substrates.
  12. Zhang, Xunyuan; Xie, Ruilong; Lin, Sean X., Method of forming a gate contact structure for a semiconductor device.
  13. Xie, Ruilong; Park, Chanro; Sung, Min Gyu; Kim, Hoon, Method of forming a semiconductor device with a gate contact positioned above the active region.
  14. Besser Paul R. ; Kepler Nick ; Wieczorek Karsten,DEX, Method of forming junction leakage free metal silicide in a semiconductor wafer by alloying refractory metal.
  15. van der Putten Andreas M. T. P. (Eindhoven NLX), Method of manufacturing a semiconductor device.
  16. Lopatin Sergey ; Nogami Takeshi ; Pramanik Shekhar, Method of metal/polysilicon gate formation in a field effect transistor.
  17. Vashchenko, Vladislav; Hopper, Peter J.; Lindorfer, Philipp; Strachon, Andy; Johnson, Peter, Method of providing semiconductor interconnects using silicide exclusion.
  18. LaPlante, Mark J.; Casey, Jon A.; Wassick, Thomas A.; Long, David C.; Semkow, Krystyna W.; Spencer, Patrick E.; Rita, Robert A.; Indyk, Richard F.; Wiley, Kathleen M.; Sundlof, Brian R.; Balz, James;, Method of selective plating on a substrate.
  19. Zhou Mei Sheng,SGX ; Xu Guo-Qin,SGX ; Chan Lap, Method to deposit a platinum seed layer for use in selective copper plating.
  20. Sinha, Nishant, Methods for forming conductive vias in semiconductor device components.
  21. Sinha, Nishant, Methods for forming conductive vias in semiconductor device components.
  22. Sinha, Nishant, Methods for forming conductive vias in semiconductor device components.
  23. Siew, Yongkong; Park, Seongho, Methods of fabricating a semiconductor device having a via structure and an interconnection structure.
  24. Siew, Yongkong; Park, Seongho, Methods of fabricating a semiconductor device having a via structure and an interconnection structure.
  25. Farnworth, Warren M.; McDonald, Steven M.; Sinha, Nishant; Hiatt, William M., Methods of fabricating substrates including at least one conductive via.
  26. Farnworth,Warren M.; McDonald,Steven M.; Sinha,Nishant; Hiatt,William M., Methods of fabricating substrates including at least one conductive via.
  27. Farnworth, Warren M.; McDonald, Steven M.; Sinha, Nishant; Hiatt, William M., Methods of fabricating substrates including one or more conductive vias.
  28. Wai,Chien M.; Ohde,Hiroyuki; Kramer,Steve, Methods of forming metal-containing films over surfaces of semiconductor substrates.
  29. Kirby,Kyle K.; Farnworth,Warren M., Methods of plating via interconnects.
  30. Mathew, Varughese; Acosta, Eddie; Chatterjee, Ritwik; Garcia, Sam S., Micropad for bonding and a method therefor.
  31. Mathew, Varughese; Acosta, Eddie; Chatterjee, Ritwik; Garcia, Sam S., Micropad formation for a semiconductor.
  32. Sinha,Nishant, Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias.
  33. Wai,Chien M.; Ohde,Hiroyuki; Kramer,Steve, Semiconductor constructions.
  34. Wai,Chien M.; Ohde,Hiroyuki; Kramer,Steve, Semiconductor constructions comprising a layer of metal over a substrate.
  35. Sinha, Nishant, Semiconductor device components with conductive vias and systems including the components.
  36. Xie, Ruilong; Park, Chanro; Sung, Min Gyu; Kim, Hoon, Semiconductor device with a gate contact positioned above the active region.
  37. Kirby, Kyle K.; Farnworth, Warren M., Semiconductor devices and in-process semiconductor devices having conductor filled vias.
  38. Pan, James N.; Sun, Sey-Ping; Waite, Andrew M., Strain enhanced semiconductor devices and methods for their fabrication.
  39. Chidambarrao, Dureseti; Radens, Carl, Structure and method for MOSFET with reduced extension resistance.
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