초록 ▼

A memory cell is provided having reduced read and write times, and a large current differential between the standby mode and the read mode. A pair of cross-coupled NPN transistors have their emitters coupled to a lower word line and their collectors coupled to an upper word line by a first and secon

A memory cell is provided having reduced read and write times, and a large current differential between the standby mode and the read mode. A pair of cross-coupled NPN transistors have their emitters coupled to a lower word line and their collectors coupled to an upper word line by a first and second load, respectively. First and second NPN sense transistors each have a base coupled to the base of one of the cross-coupled transistors, an emitter coupled to a first and a second bit line, respectively, and a collector coupled to receive a supply voltage.

대표청구항 ▼

A memory cell having a first bit line, a second bit line, a first word line, and a second word line, comprising: a voltage terminal; a first load; a second load; a pair of latchable cross-coupled transistors having their emitters coupled to said second word line, their collectors coupled to said fir

A memory cell having a first bit line, a second bit line, a first word line, and a second word line, comprising: a voltage terminal; a first load; a second load; a pair of latchable cross-coupled transistors having their emitters coupled to said second word line, their collectors coupled to said first word line by said first and second loads, respectively, and their bases coupled to each other\s collector; first means coupled between said voltage terminal and said first bit line and coupled to said base of one of said pair of latchable cross-coupled transistors for sinking current from said base of said one of said pair of latchable cross-coupled transistors, wherein a voltage on said voltage terminal is greater in magnitude than the voltage on said first bit line; and second means coupled between said voltage terminal and said second bit line and coupled to said base of the other of said pair of latchable crosscoupled transistors for sinking current from said base of said other of said pair of latchable cross-coupled transistors, wherein a voltage on said voltage terminal is greater in magnitude than the voltage on said second bit line.