초록 ▼

A delay circuit for a gate-array LSI including at least one inverter having a plurality of P-channel transistors (Q1p to Q4p) and a plurality of N-channel transistors (Q1n to Q4n) connected in series. The P-channel/N-channel transistors are driven by an input potential (IN), and the common output of

A delay circuit for a gate-array LSI including at least one inverter having a plurality of P-channel transistors (Q1p to Q4p) and a plurality of N-channel transistors (Q1n to Q4n) connected in series. The P-channel/N-channel transistors are driven by an input potential (IN), and the common output of the innermost pair of P-channel/N-channel transistors generates an output.

대표청구항 ▼

A delay circuit comprising: an input terminal (IN); an intermediate terminal (C); an output terminal (OUT); first and second power supply means (Vcc, GND); a first inverter (INVA) connected between said input terminal and said intermediate terminal, said first inverter comprising: a plurality of fir

A delay circuit comprising: an input terminal (IN); an intermediate terminal (C); an output terminal (OUT); first and second power supply means (Vcc, GND); a first inverter (INVA) connected between said input terminal and said intermediate terminal, said first inverter comprising: a plurality of first P-channel transistors (Q1p to Q4p) connected in series between said first power supply means and said intermediate terminal, said first P-channel transistors being driven by the potential at said input terminal; a plurality of first N-channel transistors (Q1n to Q4n) connected in series between said intermediate terminal and said second power supply terminal, said first N-channel transistors being driven by the potential at said input terminal; and a second inverter (INVB) connected between said intermediate terminal and said output terminal, said second inverter comprising: a plurality of second P-channel transistors to (Q1p′to Q4p′) connected in series between said first power supply means and said output terminal, said second P-channel transistors being driven by the potential at said intermediate terminal, and a plurality of second N-channel transistors (Q1n′to Q4n′) connected in series between said output terminal and said second power supply terminal, said second N-channel transistors being driven by the potential at said intermediate terminal.