$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Interface circuit arrangement for transferring data from a master processor to a slave processor

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/16
  • G06F-011/16
  • G06F-012/00
출원번호 US-0458252 (1983-01-17)
우선권정보 IT-0019173 (1982-01-19)
발명자 / 주소
  • Campanini Giorgio (Bareggio ITX)
출원인 / 주소
  • Italtel Societa Italiana Telecomunicazioni SpA (Milan ITX 03)
인용정보 피인용 횟수 : 76  인용 특허 : 12

초록

Two identical processors of a communication system, operating in master-slave relationship, each have a mass memory, a working memory, a CPU and an interface interlinked by an internal bus, the two interfaces being interconnected by an interprocessor bus serving for the exchange of data therebetween

대표청구항

In a data-handling system with first and second processors which are substantially identical with said first processor operated in a master function referred to as a master processor, said second processor operated in a slave function referred to as a slave processor, said second processor being an

이 특허에 인용된 특허 (12)

  1. Larson Allen L. (Thornton CO), Channel interface circuit with high speed data message header field translation and direct memory access.
  2. Southard Gary (Coral Springs FL), Cross channel circuit for an electronic system having two or more redundant computers.
  3. Etoh Kunihiko (Toyota JPX) Ishigaki Tamotsu (Nagoya JPX) Niwa Kuniyuki (Kariya JPX), Data transfer system for data exchange between two operation processors.
  4. Horn Robert (Richardson TX), Data transmission system.
  5. Hughes Jodie K. (San Jose CA) Hagiwara Sekine (San Jose CA), Direct memory access data transfer system for use with plural processors.
  6. Harris Craig W. (El Toro CA), Direct memory access logic system for a data transfer network.
  7. Marsh Phillip W. (Granger UT) Wiedenman Gregory B. (Sandy UT), Error detection system.
  8. Giallanza Frank V. (San Jose CA) Tracey Don M. (Mountain View CA) Holcombe Wayne T. (Palo Alto CA), Message communication system with message storage.
  9. Persaud Ian K. (Lodi NJ) Heinemann Joseph B. (New York NY), Multi-processor system.
  10. Richer Donald K. (Mansfield MA), Process control system with improved system security features.
  11. Giorcelli Silvano (Turin IT), System for checking two data processors operating in parallel.
  12. Schneider Lutz (Malsch-Vlkersbach DEX) Guigas Bruno (Bruchsal DEX), Transferring data between memory and magnetic storage.

이 특허를 인용한 특허 (76)

  1. Long,Finbarr Denis; Ardini,Joseph; Kirkpatrick,Dana A.; O'Keeffe,Michael James, Apparatus and methods for fault-tolerant computing using a switching fabric.
  2. Edwards, Jr., John W., Apparatus and methods for identifying bus protocol violations.
  3. Morton John D. (Nepean CAX) Newcombe Edmund A. (Ottawa CAX) Lander Emil (Nepean CAX), Automatic refresh of operating parameters in equipment with volatile storage.
  4. MacLeod, John, Caching for I/O virtual address translation and validation using device drivers.
  5. Soya Takashi,JPX ; Sekiya Toshiyuki,JPX, Communication apparatus for communicating with a plurality of communication control units cascade-connected.
  6. Gatti Joe D. ; Ewing William R., Configuration control system for configuring multiple biomedical devices.
  7. Doody, John W.; Long, Finbarr Denis; McLoughlin, Michael; O'Keefe, Michael James, Coordinated recalibration of high bandwidth memories in a multiprocessor computer.
  8. Nakayama Takashi (Tokyo JPX), Coprocessor having a slave processor capable of checking address mapping.
  9. Kadoya Hitoshi,JPX, Data processing apparatus having a sorting unit to provide sorted data to a processor.
  10. Shinjo Naoki (Kawasaki JPX) Nagasawa Shigeru (Kawasaki JPX) Ikeda Masayuki (Kawasaki JPX) Ueno Haruhiko (Kawasaki JPX) Utsumi Teruo (Kawasaki JPX) Kobayakawa Kazushige (Kawasaki JPX) Dewa Masami (Kaw, Data processing unit.
  11. Hirokawa Masayuki (Hyogo JPX), Data transfer control units each of which comprises processors and dual-part memory.
  12. Yamamoto Akito (Yokohama JPX) Ueno Takashi (Yokosuka JPX) Sumizawa Akio (Yokosuka JPX), Device for interfacing data communications.
  13. Savage Shaun V. (Bountiful UT) Harris Johnny M. (Woods Cross UT), Direct memory access controller with direct memory to memory transfers.
  14. Braun Fritz,DEX ; Finsterbusch Joachim,DEX ; Decius Nikolaus,DEX, Electronic apparatus, process for its duplication, and arrangement for data transfer between two similarly constructed.
  15. Somers, Jeffrey S.; Huang, Wen-Yi; Tetreault, Mark D.; Wegner, Timothy M., Fault-tolerant computer system with voter delay buffer.
  16. Suffin, A. Charles; Amato, Joseph S.; Joyce, Paul, Fault-tolerant maintenance bus architecture.
  17. Suffin, A. Charles, Fault-tolerant maintenance bus protocol and method for using the same.
  18. Krings Lothar (Baden CHX), Fault-tolerant multiprocessor arrangement.
  19. Sinha, Navendu; Jordan, William Charles; Moyer, Bryon Irwin; Fricke, Stephen John Joseph; Attias, Roberto; Deshpande, Akash Renukadas; Gupta, Vineet; Sonakiya, Shobhit, Generating hardware accelerators and processor offloads.
  20. Sinha, Navendu; Jordan, William Charles; Moyer, Bryon Irwin; Fricke, Stephen John Joseph; Attias, Roberto; Deshpande, Akash Renukadas; Gupta, Vineet; Sonakiya, Shobhit, Generating hardware accelerators and processor offloads.
  21. Sinha, Navendu; Jordan, William Charles; Moyer, Bryon Irwin; Fricke, Stephen John Joseph; Attias, Roberto; Deshpande, Akash Renukadas; Gupta, Vineet; Sonakiya, Shobhit, Hardware accelerator test harness generation.
  22. Catlin Gary M. (Cupertino CA), Hardwired pipeline processor for logic simulation.
  23. Yu Ying-King, High availability network disk mirroring system.
  24. Funakubo Nobuo (Hadano JPX), Logic operation device.
  25. Olson, Thomas M., Maintenance of consistent, redundant mass storage images.
  26. Amini Nader (Boca Raton FL) Horne Richard Louis (Boynton Beach FL), Method and apparatus for determining address location and taking one of two actions depending on the type of read/write.
  27. Somers, Jeffrey; Alden, Andrew; Edwards, John, Method and apparatus for efficiently moving portions of a memory block.
  28. Flockhart, Andrew D.; Howell, Christopher Robinson; Mathews, Eugene P.; Romero, Chadwick Joseph, Method and apparatus for global call queue in a global call center.
  29. Ackerman Joseph R. ; Karg Kenneth A. ; Patel Angela C., Method and apparatus for initializing an automated train control system.
  30. Deur,Michael W.; Hayner,David; Tietjen,Donald Louis, Method and apparatus for interconnecting portions of circuitry within a data processing system.
  31. Bergsten, Bjorn; Mutalik, Praveen G., Method and apparatus for managing session information.
  32. Liddell David C. (Tyne & Wear GBX) Williams Emrys J. (Milton Keynes GBX), Method and apparatus for reducing the effects of hardware faults in a computer system employing multiple central process.
  33. Flockhart,Andrew D.; Roybal,Larry John; Steiner,Robert C., Method and apparatus for scheduling tasks.
  34. Olson, Thomas, Method and apparatus for storing transactional information in persistent memory.
  35. Dan Asit ; Kienzle Martin Gerhard ; Sitaram Dinkar ; Yu Philip Shi-lung, Method and system for load balancing by replicating a portion of a file being read by a first stream onto second device and reading portion with a second stream capable of accessing.
  36. Somers, Jeffrey S.; Tetreault, Mark D.; Wegner, Timothy M., Method and system for upgrading fault-tolerant systems.
  37. Bohlin, Lars, Method for supervising parallel processes.
  38. Tetreault,Mark, Methods and apparatus for computer bus error termination.
  39. Catlin Gary M. (Cupertino CA), Multiple processor accelerator for logic simulation.
  40. Catlin Gary M. (Cupertino CA), Multiple processor accelerator for logic simulation.
  41. Ezzet Ali (Sunnyvale CA), Multiple segmenting of main memory to streamline data paths in a computing system.
  42. Novy Robert (Redwood City CA) Guyon Richard (Mt. View CA) Chimenti Moreno A. (Rome ITX), Multiple sup swap mechanism.
  43. Hashiguchi Tatsuro (Tokyo JPX), Multiprocessor system with storage control units including buffer storage units comprising an error recovery system for.
  44. Verbanets ; Jr. William R. (Plum Borough PA), Multipurpose digital IC for communication and control network.
  45. Stolero, Simon; Holtzman, Micky; Pinto, Yosi; Elhamias, Reuven; Azari, Meiri, Non-volatile memory system with self test capability.
  46. Stolero, Simon; Holtzman, Micky; Pinto, Yosi; Elhamias, Reuven; Azari, Meiri, Non-volatile memory system with self test capability.
  47. Fricke, Stephen John Joseph; Jordan, William Charles; Moyer, Bryon Irwin; Attias, Roberto; Deshpande, Akash Renukadas; Sinha, Navendu; Gupta, Vineet; Sonakiya, Shobhit, Packet ingress/egress block and system and method for receiving, transmitting, and managing packetized data.
  48. Beatty Harry John ; Elmendorf Peter Claude ; Gillis Roland Roberto ; Pramanick Ira, Parallel execution of a complex task partitioned into a plurality of entities.
  49. Vachon Guy (Austin TX), Peripheral I/O bus and programmable bus interface for computer data acquisition.
  50. Matsushiba Takuji,JPX ; Karube Satoshi,JPX, Peripheral unit having at least two sequencer circuits configured to control data transfers for power saving.
  51. Hoffman Harrell (3509 Greenway Austin TX 78705) Smith Scott M. (9211 Mystic Oaks Trail Austin TX 78750) Voltin John A. (13001 Broadmeade Austin TX 78729) Wright Charles G. (1204 Woodrock Round Rock T, Processor controlled DMA controller for transferring instruction and data from memory to coprocessor.
  52. Ors, Ali Osman; Laroche, Daniel; Deschênes, Jean-François, Sequencer controlled system and method for controlling timing of operations of functional units.
  53. Chou, Norman C.; Li, Whitney, Slave device having independent error recovery.
  54. Sinha Pradeep (Ithaca NY) Rahman Turhan F. (Ithaca NY), Solid-modeling system using topology directed subdivision for determination of surface intersections.
  55. Attias, Roberto; Jordan, William Charles; Moyer, Bryon Irwin; Fricke, Stephen John Joseph; Deshpande, Akash Renukadas; Sinha, Navendu; Gupta, Vineet; Sonakiya, Shobhit, Structured block transfer module, system architecture, and method for transferring.
  56. Attias, Roberto; Jordan, William Charles; Moyer, Bryon Irwin; Fricke, Stephen John Joseph; Deshpande, Akash Renukadas; Sinha, Navendu; Gupta, Vineet; Sonakiya, Shobhit, Structured block transfer module, system architecture, and method for transferring.
  57. Attias, Roberto; Jordan, William Charles; Moyer, Bryon Irwin; Fricke, Stephen John Joseph; Deshpande, Akash Renukadas; Sinha, Navendu; Gupta, Vineet; Sonakiya, Shobhit, Structured block transfer module, system architecture, and method for transferring.
  58. Liddell David C.,GBX ; Williams Emrys J.,GBX, System and method for accessing devices in a computer system.
  59. Young David W. ; Holt Jeffrey J., System and method for controlling a slave processor.
  60. Liddell David C.,GBX ; Williams Emrys J.,GBX, System and method for detecting errors using CPU signature.
  61. Liddell David C.,GBX ; Williams Emrys J.,GBX, System and method for diagnosing errors in a multiprocessor system.
  62. Liddell, David C.; Williams, Emrys J., System and method for driving a signal to an unbuffered integrated circuit.
  63. Liddell David C.,GBX ; Williams Emrys J.,GBX, System and method for iterative copying of read/write memory.
  64. Graham, Simon P., System and method for operating a SCSI bus with redundant SCSI adaptors.
  65. Nelvin, Robert E.; Tetreault, Mark D.; Alden, Andrew; Dolaty, Mohsen; Edwards, Jr., John W.; Kement, Michael W.; MacLeod, John R., System and method for operating a system with redundant peripheral bus controllers.
  66. Liddell David C.,GBX ; Williams Emrys J.,GBX, System and method for preserving the state of a device across a reset event.
  67. Liddell David C.,GBX ; Williams Emrys J.,GBX, System and method for providing synchronous clock signals in a computer.
  68. Liddell David C.,GBX ; Williams Emrys J.,GBX, System and method for reducing the effects of hardware faults in a computer system employing multiple central processin.
  69. Liddell David C.,GBX ; Williams Emrys J.,GBX, System and method for self-referential accesses in a multiprocessor computer.
  70. Liddell David C.,GBX ; Williams Emrys J.,GBX, System and method for synchronously resetting a plurality of microprocessors.
  71. Liddell David C.,GBX ; Williams Emrys J.,GBX, System and method for tracking dirty memory.
  72. Yakushiji Hiroshi,JPX ; Osaki Tomoko,JPX ; Sato Reiko,JPX ; Iwawaki Masato,JPX, System control apparatus including a master control unit and a slave control unit which maintain coherent information.
  73. Newman, Otto R., Systems and methods for caching with file-level granularity.
  74. Niemeyer Gunter ; Slotine Jean-Jacques E., Teleoperation with variable delay.
  75. Shinjo Naoki (Kawasaki JPX) Nagasawa Shigeru (Kawasaki JPX) Ikeda Masayuki (Kawasaki JPX) Ueno Haruhiko (Kawasaki JPX) Utsumi Teruo (Kawasaki JPX) Kobayakawa Kazushige (Kawasaki JPX) Dewa Masami (Kaw, Transfer processor including a plurality of failure display units wherein a transfer process is prohibited if failure is.
  76. Urabe Yoshio,JPX ; Koga Shouichi,JPX ; Takai Hitoshi,JPX ; Kai Koji,JPX ; Yamasaki Hidetoshi,JPX, Waveform shaping method and equipment.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트