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Process for making a T-gated transistor 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/285
출원번호 US-0916592 (1986-10-08)
발명자 / 주소
  • Beaubien Randall S. (Westlake Village CA) Erps Lorri A. (Pleasanton CA)
출원인 / 주소
  • Hughes Aircraft Company (Los Angeles CA 02)
인용정보 피인용 횟수 : 27  인용 특허 : 12

초록

A process for preparing a T-gate structure for use in applying a gate voltage in a field effect transistor, wherein the gate has a short foot portion in contact with the semiconductor substrate for a short gate length and consequent low capacitance, and a large amount of metal in a contact head port

대표청구항

A process for preparing a T-gate metal structure for use in a semiconductor device, the T-gate having a foot in contact with a semiconductor substrate and an enlarged head upon the foot and integral therewith, comprising the steps of: furnishing a semiconductor substrate; depositing a dielectric lay

이 특허에 인용된 특허 (12)

  1. Chao, Pane-Chane; Ku, Walter H., Fabrication of T-shaped metal lines for semiconductor devices.
  2. Chao, Pane-Chane; Ku, Walter H., Fabrication of metal lines for semiconductor devices.
  3. Sebesta Edward H. (San Francisco CA), Lift-off process for depositing metal on a substrate.
  4. Akiyama Tatsuo (Tokyo JPX) Koshino Yutaka (Yokosuka JPX) Hiraki Shunichi (Hyogo JPX), Method of manufacturing a semiconductor device.
  5. Stockton Ronald J. (Nederland CO) Munson Robert E. (Boulder CO), Monolithic microwave integrated circuit with integral array antenna.
  6. Jambotkar Chakrapani G. (Hopewell Junction NY) Malaviya Shashi D. (Fishkill NY), One mask technique for substrate contacting in integrated circuits involving deep dielectric isolation.
  7. Shibata Hiroshi (Kanagawa JPX), Pattern forming method.
  8. Tan Tun S. (Santa Rosa CA), Pre-passivated sub-micrometer gate electrodes for MESFET devices.
  9. Kim Kwang K. (Poughkeepsie NY), Process for applying closely overlapped mutually protective barrier films.
  10. Lee William W. Y. (Fountain Valley CA) Shaw Gareth L. (Fountain Valley CA) Clayton ; deceased James W. (late of Santa Ana CA) Bachino ; administrator Denise (Santa Maria CA), Process for fabricating multi-level-metal integrated circuits at high yields.
  11. Kim Bumman (Richardson TX) Saunier Paul (Garland TX), Process for forming a T-shaped gate structure.
  12. Coane Philip J. (Mahopac NY), Process for forming semiconductor devices using electron-sensitive resist patterns with controlled line profiles.

이 특허를 인용한 특허 (27)

  1. Subramanian,Ramkumar; Lyons,Christopher F.; Plat,Marina V.; Singh,Bhanwar, Damascene process for a T-shaped gate electrode.
  2. Fix, Richard; Wolst, Oliver; Martin, Alexander, Electronic component with diffusion barrier layer.
  3. Hsu, Chin-Tsai; Chen, Chi-Jui; Liu, Pang-Miao, Gate structure forming method of field effect transistor.
  4. Green, Bruce M.; Moore, Karen E.; Hartin, Olin, High speed gallium nitride transistor devices.
  5. Green, Bruce M.; Moore, Karen E.; Hartin, Olin, High speed gallium nitride transistor devices.
  6. Jain, Kanti; Chae, Junghun; Appasamy, Sreeram, High throughput, low cost dual-mode patterning method for large area substrates.
  7. Jain, Kanti; Chae, Junghun, Material assisted laser ablation.
  8. Jain, Kanti; Reddy, Uttam, Method for fabricating dual damascene profiles using sub pixel-voting lithography and devices made by same.
  9. Lee Jin-Hee (Daejeon KRX) Choi Sang-Soo (Daejeon KRX) Youn Hyung-Sup (Daejeon KRX) Park Chul-Soon (Daejeon KRX) Yoo Hyung-Jun (Daejeon KRX) Park Hyung-Moo (Daejeon KRX), Method for making T-gate of field effect transistor.
  10. Jo Jun Whan,KRX, Method for manufacturing self-aligned T-type gate.
  11. Kamiyama Tomoyuki,JPX ; Ishikawa Yamato,JPX, Method of forming a high-frequency transistor T gate electrode.
  12. Morikawa Hiroshi (Tokyo JPX), Method of making a field effect transistor with overlay gate structure.
  13. Chen Yen-Ming,TWX ; Liu Wei-Jen,TWX ; Lin Shih-Chi,TWX ; Liu Kuo-Chou,TWX, Method of manufacturing self-aligned T-shaped gate through dual damascene.
  14. Jain, Kanti; Reddy, Uttam, Methods for fabricating complex micro and nanoscale structures and electronic devices and components made by the same.
  15. Smith, Richard Peter; Sheppard, Scott T., Methods of fabricating transistors including dielectrically-supported gate electrodes.
  16. Smith, Richard Peter; Sheppard, Scott T., Methods of fabricating transistors including dielectrically-supported gate electrodes and related devices.
  17. Sheppard, Scott T.; Allen, Scott, Methods of fabricating transistors including supported gate electrodes.
  18. Jain, Kanti; Lin, Kevin, Patterning methods for stretchable structures.
  19. Sun Shih-Wei (Austin TX) Woo Michael P. (Austin TX), Process for forming a feature on a substrate without recessing the surface of the substrate.
  20. Cohen, Guy A.; Cordes, Steven A.; Goma, Sherif A.; Rosner, Joanna; Trewhella, Jeannine M., Processing for overcoming extreme topography.
  21. Cohen, Guy M.; Cordes, Steven A.; Goma, Sherif A.; Rosner, Joanna; Trewhella, Jeannine M., Processing for overcoming extreme topography.
  22. Choi, Sang Soo; Lee, Jim Hee; Kim, Doh Hoon; Lee, Kag Hyeon; Chung, Hai Bin; Kim, Dae Yong, Structure and process method of gamma gate for HEMT.
  23. Marina Plat ; Christopher F. Lyons ; Bhanwar Singh ; Ramkumar Subramanian, T or T/Y gate formation using trim etch processing.
  24. Yoo Hyung Mo ; Nguyen Xuan,KRX, T-gate MESFET process using dielectric film lift-off technique.
  25. Maoz Barak (Highland Park NJ), Variable attenuator having voltage variable FET resistor with chosen resistance-voltage relationship.
  26. Maoz Barak (Highland Park NJ), Voltage variable FET resistor with chosen resistance-voltage relationship.
  27. Pan Yang,SGX ; Liu Erzhuang,SGX, Way to fabricate the self-aligned T-shape gate to reduce gate resistivity.
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