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Bonding pad interconnection structure

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-007/10
출원번호 US-0809448 (1985-12-16)
발명자 / 주소
  • Takiar Hem P. (San Jose CA) George Thomas (Albany CA)
출원인 / 주소
  • National Semiconductor Corporation (Santa Clara CA 02)
인용정보 피인용 횟수 : 78  인용 특허 : 12

초록

Semiconductor devices having bonding pads formed over active regions on the device are fabricated by providing protective layers between the bonding pad and the underlying active region(s). The first protective layer is formed from a polyimide material which can absorb shock resulting from tape auto

대표청구항

A semiconductor device comprising: a substrate having a surface upon which is located at least one metallization pad; a polyimide layer formed over said surface and said metallization pad; a puncture-resistant layer formed over said polyimide layer a metal interconnect vertically penetrating both th

이 특허에 인용된 특허 (12)

  1. Burns Carmen D. (San Jose CA), Assembly tape for hermetic tape packaging semiconductor devices.
  2. Hosack Harold H. (Cupertino CA), Edge etch method for producing narrow openings to the surface of materials.
  3. Burns Carmen D. (San Jose CA), Gang bonding interconnect tape process and structure for semiconductor device automatic assembly.
  4. Burns Carmen D. (San Jose CA), Integrated circuit packaging process.
  5. Farrar Paul A. (South Burlington VT) Geffken Robert M. (Burlington VT) Kroll Charles T. (Raleigh NC), Method for forming dense multilevel interconnection metallurgy for semiconductor devices.
  6. Barth Phillip W. (Palo Alto CA), Method of fabrication of long arrays using a short substrate.
  7. Chang Kenneth (Hopewell Junction NY) Cosman David C. (Newburgh NY) Gartner Helmut M. (Wappingers Falls NY) Hoeg ; Jr. Anthony J. (Wappingers Falls NY), Method of forming thin film interconnection systems.
  8. Raffel Jack I. (Lexington MA) Yasaitis John A. (Lexington MA) Chapman Glenn H. (Bedford MA) Naiman Mark L. (Lincoln MA), Method of making a conductive path in multi-layer metal structures by low power laser beam.
  9. Abbas Shakir A. (Wappingers Falls NY) Magdo Ingrid E. (Hopewell Junction NY), Method to fabricate stud structure for self-aligned metallization.
  10. Balda Raymond J. (Tempe AZ) Bukhman Yefim (Tempe AZ) Goodner Willis R. (Chandler AZ), Process for fabricating semiconductor device.
  11. Burns Carmen D. (San Jose CA), Process for hermetically encapsulating semiconductor devices.
  12. Burns Carmen D. (San Jose CA), Tape operated semiconductor device packaging.

이 특허를 인용한 특허 (78)

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  2. Subramanion Ramkumar ; Pangrle Suzette K. ; Pellerin John G. ; Gallardo Ernesto A., Anti-reflective coating layer for semiconductor device.
  3. Zambrano Raffaele,ITX, Bonding pad for a semiconductor chip.
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  6. Kuo, Nick; Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Chu-Fu, Chip structure with bumps and testing pads.
  7. Lin,Shih Hsiung; Lin,Mou Shiung, Circuit component with bump formed over chip.
  8. Hashimoto, Nobuaki, Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument.
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  31. Pozder, Scott K.; Kobayashi, Thomas S., Method for forming a semiconductor device having a mechanically robust pad interface.
  32. Lee,Jin Hyuk; Kim,Gu Sung; Lee,Dong Ho; Jang,Dong Hyeon, Method for manufacturing a wafer level chip scale package.
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  41. Singh,Inderjit; Marks,Howard Lee; Greco,Joseph David, Pad over active circuit system and method with frame support structure.
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  50. Kazutami Arimoto JP, Semiconductor chip scale package and ball grid array structures.
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  52. Eimori, Takahisa; Kimura, Hiroshi, Semiconductor device and manufacturing process thereof.
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  54. Eimori Takahisa,JPX ; Kimura Hiroshi,JPX, Semiconductor device having self-aligned contacts.
  55. Utpal Kumar Chakrabarti ; Bora M Onat ; Kevin Cyrus Robinson ; Biswanath Roy ; Ping Wu, Semiconductor devices which utilize low K dielectrics.
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  57. Seshan,Krishna; Dass,M. Lawrence A.; Bakker,Geoffrey L., Semiconductor passivation deposition process for interfacial adhesion.
  58. Thomas, Danielle A.; Siegel, Harry Michael; Do Bento Vieira, Antonio A.; Chiu, Anthony M., System for providing a redistribution metal layer in an integrated circuit.
  59. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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