[특허]Distributed cache in dynamic rams

Distributed cache in dynamic rams 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G11C-007/00
출원번호	US-0651562 (1984-09-18)
발명자 / 주소	Kronstadt Eric P. (Westchester County NY) Gandhi Sharad P. (Santa Clara CA)
출원인 / 주소	International Business Machines Corp. (Armonk NY 02)
인용정보	피인용 횟수 : 82 인용 특허 : 0

초록 ▼

A microcomputer memory system is organized into a plurality of banks (16). Each back consists of an array of static column mode dynamic random access memories (DRAMs) of the type having an on-chip static buffer for storing an entire row. The static buffers associated with each bank functions as a distributed cache (24) to hold the last accessed row for the associated bank. A memory controller (18) receives real addresses from a CPU (10) or other device on the memory bus (14) and extracts bank and row numbers from the address. The memory controller determines whether the accessed row for a memory bank is in the distributed cache and, if it is, accesses the distributed cache for that bank. Otherwise, the memory controller switches the contents of the distributed cache with the contents of the addressed row for that bank.

대표청구항 ▼

A computer memory system comprising: a plurality of memory chips organized into a plurality of banks, each memory chip having a matrix of m rows by n columns of memory cells accessed by a row address select signal and a row number address, each bank consisting of an array of static column mode dynamic random access memory chips of the type having an on-chip static buffer for storing an entire row of data of a corresponding row in said memory cell matrix accessed by the row address select signal and a row number address, the static buffers associated with each bank functioning as a distributed cache to hold the last accessed row for the associated bank, the data in the distributed cache corresponding to one of said plurality of banks being accessed by a column address select signal and a column address for that bank; and a memory controller included in said computer memory system for receiving real addresses and connected to the memory banks to access the dynamic random access memory chips for read and write and refresh operations, said memory controller including: refresh means for periodically refreshing said dynamic random access memory chips, table means for maintaining first and second fields, said first field containing the number of the row which is currently in the distributed cache for each bank and said second field containing valid entry flags for the distributed cache of each bank, said valid entry flags being set to valid for a bank when a row of data is read into the distributed cache in response to a row address select signal and a row number address and being set to invalid after power-on and following a refresh operation in a bank, and accessing means for receiving real addresses and accessing the dynamic random access memory chips for read and write operations, said accessing means extracting bank and row numbers from an address and if an accessed row for that bank is in the distributed cache as indicated by said first field with a valid entry flag set in said second field of said table means, generating a column address and activating the column address select signal for that bank, otherwise inactivating and then activating again the row address select signal for that bank with the row number of a new address to write back the distributed cache contents into the dynamic random access memory cell matrix and load a new row of data for that bank into the distributed cache.

이 특허를 인용한 특허 (82)

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Distributed cache in dynamic rams 원문보기

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Distributed cache in dynamic rams 원문보기

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