$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Chip on board package for integrated circuit devices using printed circuit boards and means for conveying the heat to th 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-007/20
출원번호 US-0866528 (1986-05-23)
발명자 / 주소
  • Brown Candice H. (San Jose CA)
출원인 / 주소
  • Advanced Micro Devices, Inc. (Sunnyvale CA 02)
인용정보 피인용 횟수 : 114  인용 특허 : 0

초록

The invention discloses an improved PC board package for at least one integrated circuit die utilizing a plurality of PC boards bonded together to form a composite. The composite has at least one cavity, for mounting of an integrated circuit die, formed in at least one PC board of the composite. The

대표청구항

An improved PC board package containing at least one integrated circuit die mounted therein comprising: (a) a plurality of PC board laminates bonded together to form a composite; (b) at least one cavity, having said integrated circuit die mounted therein, formed in at least a first of said plurality

이 특허를 인용한 특허 (114)

  1. Daniel N. Donahoe ; Michael T. Gill, Apparatus for liquid cooling of specific computer components.
  2. Donahoe Daniel N. ; Gill Michael T., Apparatus for liquid cooling of specific computer components.
  3. Huemoeller, Ronald Patrick; Kelly, Michael; Hiner, David Jon, Backside warpage control structure and fabrication method.
  4. Shirakawa Hirotsugu,JPX ; Tanaka Yasunori,JPX, Bear chip mounting printed circuit board and a method of manufacturing thereof by photoetching.
  5. Deshpande Narayan V. (Penfield NY) Ims Dale R. (Webster NY) Hermanson Herman A. (Penfield NY) Kneezel Gary A. (Webster NY) Markham Roger G. (Webster NY), Bubble jet printing device with improved printhead heat control.
  6. Do, Won Chul; Ko, Yong Jae, Conductive pad on protruding through electrode.
  7. Do, Won Chul; Ko, Yong Jae, Conductive pad on protruding through electrode semiconductor device.
  8. Do, Won Chul; Ko, Yong Jae, Conductive pad on protruding through electrode semiconductor device.
  9. Akram Salman, Device and method for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications.
  10. Salman Akram, Device and method for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications.
  11. Akram Salman, Device for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications.
  12. Berry, Christopher John; Huemoeller, Ronald Patrick; Hiner, David Jon, Direct-write wafer level chip scale package.
  13. Berry, Christopher John; Huemoeller, Ronald Patrick; Hiner, David Jon, Direct-write wafer level chip scale package.
  14. Berry, Christopher John; Huemoeller, Ronald Patrick; Hiner, David Jon, Direct-write wafer level chip scale package.
  15. Hara, Yasuhiro; Nakayama, Takuya; Saito, Mitsuru, Electrical junction box.
  16. Rist Bruno A. (Woodland Hills CA) Casanova Alberto L. (Van Nuys CA), Electro-optical light beam signal transmission system.
  17. Akasegawa, Akihiko; Masuda, Satoshi, Electronic apparatus, method of making the same, and transceiving device.
  18. Craft Scott (Phoenix AZ), Electronic assembly having enhanced heat dissipating capabilities.
  19. Belopolsky Yakov (Hockessin DE), Electronic assembly with optimum heat dissipation.
  20. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Electronic component package comprising fan-out and fan-in traces.
  21. Andrews, Peter S.; Lowes, Theodore D.; Underwood, Robert D., Electronic device submounts with thermally conductive vias and light emitting devices including the same.
  22. Hsu, Shih-Ping, Embedded chip package structure with chip support protruding section.
  23. Huemoeller, Ronald Patrick; Kelly, Michael; Hiner, David Jon, Embedded component package and fabrication method.
  24. Huemoeller, Ronald Patrick; Kelly, Michael; Hiner, David Jon, Embedded component package and fabrication method.
  25. Huemoeller, Ronald Patrick; Rusli, Sukianto; Hiner, David J., Embedded electronic component package.
  26. Huemoeller, Ronald P.; Rusli, Sukianto; Hiner, David Jon, Embedded electronic component package fabrication method.
  27. Scanlan, Christopher M.; St. Amand, Roger D.; Kim, Jae Dong, Fan out build up substrate stackable package and method.
  28. Greenberg, Robert J.; Talbot, Neil Hamilton; Neysmith, Jordan Matthew; Ok, Jerry, Flexible circuit electrode array and method of manufacturing the same.
  29. Dekker, Ronald; Michielsen, Theodorus Martinus, Flexible device and method of manufacturing the same.
  30. Tuominen, Risto; Palm, Petteri, Heat conduction from an embedded component.
  31. Reifel Harry C. (Topsfield MA) Erdag Eren (Somerville MA) Soerewyn Herman V. D. (Peabody MA), Hermetically sealed, surface mountable component and carrier for semiconductor devices.
  32. Iovdalsky Viktor Anatolievich,RUX, Hybrid high-power integrated circuit.
  33. Fu, Huili; Sham, Man Lung; Chung, Chang-Hwa, IC packages with internal heat dissipation structures.
  34. Wieloch Christopher J., Insulated surface mount circuit board construction.
  35. Yoon, In Sang; Lee, SeongMin; Song, Sungmin, Integrated circuit package system and method of package stacking.
  36. Suzaki Hidefumi,JPX, Integrated dielectric substrate.
  37. Fuentes, Ruben; Dunlap, Brett, Integrated passive device structure and method.
  38. Boyko, Christina M.; Farquhar, Donald S.; Papathomas, Konstantinos I., Interconnect structure and method of making same.
  39. Baroky, Tajul Arosh; Chua, Janet Bee Yin, Light source device and method of making the device.
  40. Orr, Chris Erwin; Slaton, David S., Method and system for extracting heat from electrical components.
  41. Tuominen, Risto; Iihola, Antti; Palm, Petteri, Method for manufacturing a circuit board structure, and a circuit board structure.
  42. Schneider Mark R. ; Joroski Joseph, Method of assembling a heat sink assembly.
  43. Monroe, Robert W., Method of attaching a high power surface mount transistor to a printed circuit board.
  44. Dunlap, Brett Arnold, Method of forming a plurality of electronic component packages.
  45. Iijima, Makoto; Nukiwa, Masaru; Ueno, Seiji; Morioka, Muneharu, Method of forming an insulative substrate having conductive filled vias.
  46. Ozawa Takashi (Kawasaki JPX) Sorimachi Haruo (Kawasaki JPX), Method of making a multi-chip module having an improved heat dissipation efficiency.
  47. Takada, Masaru; Tsukada, Kiyotaka; Kobayashi, Hiroyuki; Minoura, Hisashi; Ukai, Yoshikazu; Kondo, Mitsuhiro, Method of manufacturing a printed wiring board having a previously formed opening hole in an innerlayer conductor circuit.
  48. Katchmar Roman (Ottawa CAX), Methods of making printed circuit boards and heat sink structures.
  49. Li, Zhihua; Hsieh, Cheng-Chieh; Hu, Jack; Erturk, Hakan; Chen, George, Microfins for cooling an ultramobile device.
  50. Hsu, Shih Ping, Multi-layer circuit board with fine pitches and fabricating method thereof.
  51. Gertiser, Kevin M.; Ripple, Richard A.; Lowry, Michael J.; Schten, Karl A.; Shearer, Ronald M.; Spall, Jim M., Multi-layer electrically isolated thermal conduction structure for a circuit board assembly.
  52. Rich ; III Edward L. (Arnold MD), Multi-layer single substrate microwave transmit/receive module.
  53. Lauffer John M. ; Magnuson Roy H. ; Markovich Voya R. ; Welsh John A., Multi-voltage plane, multi-signal plane circuit card with photoimageable dielectric.
  54. Naito, Yasuyuki; Taniguchi, Masaaki; Kuroda, Yoichi; Hori, Haruo; Figueroa, David G.; Rodriguez, Jorge P.; Watts, Nicholas R.; Holmberg, Nicholas L.; Hioki, Takashi, Multilayer capacitor, wiring board, decoupling circuit, and high frequency circuit incorporating the same.
  55. Noda Yuji,JPX, Multilayer circuit board unit.
  56. Sahara, Takahiro; Kobayashi, Atsushi; Takeuchi, Kiyoshi; Igaue, Masahiko, Multilayered printed wiring board.
  57. Nakamura, Jyunichi; Kodaira, Tadashi; Matsumoto, Shunichiro; Aratani, Hironari; Tabuchi, Takanori; Chino, Takeshi, Multilayered substrate for semiconductor device.
  58. Figueroa, David G.; Chakravorty, Kishore K.; Do, Huong T.; Mosley, Larry Eugene; Rodriguez, Jorge Pedro; Brown, Ken, Multiple tier array capacitor.
  59. Malladi Devriprasad, Package construction for integrated circuit chip with bypass capacitor.
  60. Adachi, Kazumasa; Takahashi, Shinji; Hirabayashi, Kimitaka, Package for surface mounted components.
  61. Lennartsson Mattias,SEX, Packaging material web for a self-supporting packaging container wall, and packaging containers made from the web.
  62. Nakamura Hiroshi,JPX ; Nakajima Yuji,JPX, Portable computer having a circuit board including a heat-generating IC chip and a metal frame supporting the circuit bo.
  63. Schneider Mark R., Powder metal heat sink for integrated circuit devices.
  64. Hotta, Sinichi; Takahashi, Hisaya, Printed circuit board and method for manufacturing same.
  65. Yamaguchi, Atsushi; Kumazawa, Hidehiko, Printed circuit board having through-hole protected by barrier and method of manufacturing the same.
  66. Cho,Suk Hyeon; Ryu,Chang Sup; Lee,Doo Hwan, Printed circuit board including embedded chips and method of fabricating the same using plating.
  67. Boyko Christina Marie ; Farquhar Donald Seton ; Japp Robert Maynard ; Klodowski Michael Joseph, Printed circuit board with circuitized cavity and methods of producing same.
  68. Ohyama Kazuyuki,JPX, Printed circuit board, for mounting BGA elements and a manufacturing method of a printed circuit board for mounting BGA elements.
  69. Lauffer John M. (Waverly NY) Schumacher Richard A. (Endicott NY), Printed circuit boards and cards having buried thin film capacitors and processing techniques for fabricating said board.
  70. Gohl Pierre (La Colle Sur Loup FRX) Llabres Raymond (Saint Laurent Du Var FRX) Malgouires Pascal (Cannes La Bocca FRX), Printed circuit with thermal drain.
  71. Takada, Masaru; Minoura, Hisashi; Tsukada, Kiyotaka; Kobayashi, Hiroyuki; Kondo, Mitsuhiro, Printed wiring board and method for manufacturing the same.
  72. Takada, Masaru; Minoura, Hisashi; Tsukada, Kiyotaka; Kobayashi, Hiroyuki; Kondo, Mitsuhiro, Printed wiring board and method for manufacturing the same.
  73. Takada,Masaru; Minoura,Hisashi; Tsukada,Kiyotaka; Kobayashi,Hiroyuki; Kondo,Mitsuhiro, Printed wiring board and method for manufacturing the same.
  74. Takada, Masaru; Tsukada, Kiyotaka; Kobayashi, Hiroyuki; Minoura, Hisashi; Ukai, Yoshikazu; Kondo, Mitsuhiro, Printed wiring board having throughole and annular lands.
  75. Driessen-Olde Scheper, Lamberdina; Van Acquoij, Catharinus; Ramackers, Henrikus G. M., Printhead for an image-forming apparatus and an image-forming apparatus containing the same.
  76. Kim, Sang Won; Jung, Boo Yang; Kim, Sung Kyu; Yoo, Min; Lee, Seung Jae, Semiconductor device and fabricating method thereof.
  77. Do, Won Chul; Jung, Yeon Seung; Ko, Yong Jae, Semiconductor device and manufacturing method thereof.
  78. Makoto Iijima JP; Masaru Nukiwa JP; Seiji Ueno JP; Muneharu Morioka JP, Semiconductor device and method for manufacturing substrate of the same.
  79. Do, Won Chul; Ko, Yong Jae, Semiconductor device comprising a conductive pad on a protruding-through electrode.
  80. Do, Won Chul; Jung, Yeon Seung; Ko, Yong Jae, Semiconductor device having through electrodes protruding from dielectric layer.
  81. Ishihara, Masamichi; Ooka, Fumihiko; Ino, Yoshihiko, Semiconductor device with double-sided electrode structure and its manufacturing method.
  82. Osaka,Tetsuya; Yokoshima,Tokihiko; Sato,Isao; Hashimoto,Akira; Hagiwara,Yoshio, Semiconductor multilayer wiring board and method of forming the same.
  83. Shin, Won Sun; Chun, Do Sung; Lee, Seon Goo; Shim, Il Kwon; DiCaprio, Vincent, Semiconductor package and method for fabricating the same.
  84. Shin, Won Sun; Lee, Seon Goo; Chun, Do Sung; Jang, Tae Hoan; DiCaprio, Vincent D., Semiconductor package and method for fabricating the same.
  85. Shin,Won Sun; Chun,Do Sung; Lee,Sang Ho; Lee,Seon Goo; DiCaprio,Vincent, Semiconductor package and method for fabricating the same.
  86. Shin,Won Sun; Chun,Do Sung; Lee,Soon Goo; Shim,Il Kwon; DiCaprio,Vincent, Semiconductor package and method for fabricating the same.
  87. Shin,Won Sun; Lee,Seon Goo; Chun,Do Sung; Jang,Tae Hoan; DiCaprio,Vincent, Semiconductor package and method for fabricating the same.
  88. Gerber, Mark A.; O'Connor, Shawn M.; Thompson, Trent A., Semiconductor package device for use with multiple integrated circuits in a stacked configuration and method of formation and testing.
  89. Scanlan, Christopher M.; Berry, Christopher J., Semiconductor package in package.
  90. Scanlan, Christopher M.; Berry, Christopher J., Semiconductor package in package.
  91. Ichihashi Motomi,JPX, Semiconductor sensor with protective cap covering exposed conductive through-holes.
  92. Lauffer Donald K. (San Diego CA) Sanwo Ikuo J. (San Marcos CA) Rostek Paul M. (San Diego CA), Stackable integrated circuit chip package with improved heat removal.
  93. Shin,WonSun; Chun,DoSung; Lee,SangHo; Lee,SeonGoo; DiCaprio,Vincent, Stackable semiconductor package having semiconductor chip within central through hole of substrate.
  94. Shin,Won Sun; Chun,Do Sung; Lee,Seon Goo; Shim,Il Kwon; DiCaprio,Vincent, Thin semiconductor package including stacked dies.
  95. Dunlap, Brett Arnold; Copia, Alexander William, Thin stackable package and method.
  96. Hiner, David Jon; Huemoeller, Ronald Patrick, Through via connected backside embedded circuit features structure and method.
  97. Hiner, David Jon; Huemoeller, Ronald Patrick, Through via connected backside embedded circuit features structure and method.
  98. Huemoeller, Ronald Patrick; Reed, Frederick Evans; Hiner, David Jon; Lee, Kiwook, Through via nub reveal method and structure.
  99. Huemoeller, Ronald Patrick; Reed, Frederick Evans; Hiner, David Jon; Lee, Kiwook, Through via nub reveal method and structure.
  100. Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Through via recessed reveal structure and method.
  101. Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Through via recessed reveal structure and method.
  102. Huemoeller, Ronald Patrick; Lie, Russ; Hiner, David, Two-sided fan-out wafer escape package.
  103. Budell, Timothy W.; Comino, Thomas P.; Davies, Todd W.; Keesler, Ross W.; Rosser, Steven G.; Stone, David B., Vents with signal image for signal return path.
  104. Budell,Timothy W.; Comino,Thomas P.; Davies,Todd W.; Keesler,Ross W.; Rosser,Steven G.; Stone,David B., Vents with signal image for signal return path.
  105. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  106. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  107. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  108. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  109. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  110. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  111. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  112. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  113. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package fabrication method.
  114. Higashiguchi Yutaka,JPX ; Hosogai Masao,JPX ; Otaguro Hiroyuki,JPX ; Yokemura Hitoshi,JPX ; Hida Masaharu,JPX, Wiring board with an insulating layer to prevent gap formation during etching.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로