[특허]Microwave multiport multilayered integrated circuit chip carrier

Microwave multiport multilayered integrated circuit chip carrier 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H05K-007/20
출원번호	US-0623990 (1984-06-25)
발명자 / 주소	Rowe David A. (Redondo Beach CA) Lao Binneg Y. (Rancho Palos Verdes CA) Dietterle Robert E. (Fullerton CA)
출원인 / 주소	Magnavox Government and Industrial Electronics Company (Fort Wayne IN 02)
인용정보	피인용 횟수 : 105 인용 특허 : 0

초록 ▼

A multilayered integrated circuit chip carrier has a top layer, a signal line layer, a ground layer, a power conductor layer, and a bottom layer with a separating layer between adjacent layers. Each layer has coplanar conductive and dielectric portions, the separating layers being primarily dielectric. The top layer supports an integrated circuit chip and signal launcher pads on the bottom layer couple signal and power lines of a printed circuit board to spaced points about the bottom layer periphery and substantially constant signal line impedance is achieved. The signal line layer is separated from the power conductor layer by a ground plane layer. Conductive via through pads are placed in the separating layers to form a plurality of separate conductive paths from each of the bottom and top layers to each of the signal line and power conductor layers. Via through pads are also placed in the separating layers to break up cavities and thus increase cavity resonance above signal frequencies and are placed in the signal line layer to provide signal line isolation. Thermal columns of via pads in the separating layers and conductive portions in the other layers under the chip provide chip cooling. Large grounded conductive areas in the top and bottom layers reduce unwanted signal coupling to the external environment. A capacitive coupling on the top layer between a power conductor and ground provides power line isolation.

대표청구항 ▼

Carrier apparatus for an integrated circuit chip having power and signal terminals, the carrier apparatus adapted to be mounted on a printed circuit board comprising: a printed circuit board having conductive signal lines and power lines; a plurality of superimposed layers including a top layer and a bottom layer; a signal line layer and a power conductor layer being between said top and bottom layers and separated from each other and said top and bottom layers by a respective separating layer; at least one separating layer positioned on either side of said signal line layer and on either side of said power conductor layer; said top layer having a mounting location for the chip; first and second conductive portions in said top layer adjacent the periphery of said mounting location; conductive via pads in each of said separating layers conductively coupling predetermined conductive portions of one adjacent layer to predetermined conductive portions of another adjacent layer, each of said pads being surrounded by dielectric portions of its respective separating layer; first conductive portions in said bottom layer coupling to the printed circuit board signal lines; second conductive portions in said bottom layer coupling to the printed circuit board power lines; said signal line layer having coplanar conductive signal lines each having first and second ends; said signal lines being separated by coplanar dielectric portions; said via pads comprising first via pads in respective separating layers coupling said bottom layer first conductive portions to respective first ends of respective signal lines in said signal line layer; said via pads comprising second via pads in the separating layer between said top layer and said signal line layer coupling said second ends of said signal lines to respective said first conductive portions in said top layer adjacent said mounting location; said power conductor layer having coplanar conductive power conductors separated by coplanar dielectric portions; said via pads comprising third via pads in the separating layer between said power conductor layer and said bottom layer coupling said bottom layer second conductive portions to respective conductors of said power conductors of said power conductor layer; said via pads comprising fourth via pads in respective separating layers coupling said power conductors to respective said second conductive portions of said top layer adjacent said mounting location; said separating layer having dielectric portions electrically insulating said signal lines and power conductors from each other and electrically insulating said signal lines and power conductors from said top and bottom layers.

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
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메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

연합인증

Microwave multiport multilayered integrated circuit chip carrier 원문보기

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이 특허를 인용한 특허 (105)

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Microwave multiport multilayered integrated circuit chip carrier 원문보기

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연구과제 타임라인

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