초록 ▼

A method of making an array of programmable read only semiconductor memory cells which includes forming an extra row of the memory cells and a corresponding extra row gate coupled thereto. Extra row gate enabling means is coupled to the extra row gate for enabling the extra row gate in response to a

A method of making an array of programmable read only semiconductor memory cells which includes forming an extra row of the memory cells and a corresponding extra row gate coupled thereto. Extra row gate enabling means is coupled to the extra row gate for enabling the extra row gate in response to a control signal KILLT applied thereto. A disabling means is coupled to a first selected row gate other than the extra row gate in order to disable the selected row gate in response to a control signal KILLT applied thereto. A disabling means is coupled to a first selected row gate other than the extra row gate in order to disable the selected row gate in response to the control signal KILLT being applied thereto. An NAND gate may be formed with the extra row gate to allow a second set of signals corresponding to a second selected row of memory cells to enable the second selected row gate. A disabling means is coupled to the second selected row gate other than the extra row gate. In response to a control signal KILLB being applied to both the NAND gate and to the gate of the second selected row, it is possible to use the second selected row to test the first selected row and vice versa.

대표청구항 ▼

An improved programmable read only semiconductor memory having an array of memory cells arranged in rows and columns with each row selected by a row gate which generates a row selection signal in response to a predetermined address signal received by said gate, wherein the improvement comprises: an

An improved programmable read only semiconductor memory having an array of memory cells arranged in rows and columns with each row selected by a row gate which generates a row selection signal in response to a predetermined address signal received by said gate, wherein the improvement comprises: an extra row of said memory cells; an extra row gate connected to said extra row, for enabling said extra row in response to receiving the address signal corresponding to a first one of said rows in said array and a first extra row enable signal; and means, connected to said extra row gate, for generating the first extra row enable signal in response to a first external mode control signal being at a first logic state, and for generating a first row enable signal in response to said first external mode control signal making a transition from said first logic state to a second logic state; wherein the row gate corresponding to said first one of said rows is connected to said generating means so that it enables its corresponding row responsive to receiving the address signal corresponding thereto and said first row enable signal.