초록 ▼

The medical current limiting circuit is for use with medical electrodes and associated diagnostic and therapeutic apparatus. The device protects the apparatus and patient from current flow. The device has circuitry comprising a pair of external connectors, a pair of n-type field effect transistors c

The medical current limiting circuit is for use with medical electrodes and associated diagnostic and therapeutic apparatus. The device protects the apparatus and patient from current flow. The device has circuitry comprising a pair of external connectors, a pair of n-type field effect transistors connected in cascade, a resistor, a p-type field effect transistor, a capacitor to latch the p-FET in a non-conductive state upon its initial activation and a diode to prevent capacitor discharge to the current source.

대표청구항 ▼

A two terminal, bi-directional medical current limiter device for series use with an electrode connected to the first external terminal and an electro-medical diagnostic or therapeutic apparatus connected to the second external terminal, comprising: a. first, second, third and fourth n-channel field

A two terminal, bi-directional medical current limiter device for series use with an electrode connected to the first external terminal and an electro-medical diagnostic or therapeutic apparatus connected to the second external terminal, comprising: a. first, second, third and fourth n-channel field effect transistors connected consecutively in series between the first and second external terminals, each said field effect transistor having a gate, a source and a drain terminal, said drain terminals of said first and said fourth field effect transistors being connected to the first external terminal, and the second external terminal respectively, said drain terminals of said second and said third field effect transistors being connected to said source terminals of said first and said fourth field effect transistor respectively, said gate terminals of said first and said second field effect transistors being connected to the second external terminal through said fourth field effect transistor and said gate terminals of said third and said fourth field effect transistors being connected to the first external terminal through said first field effect transistor; b. first and second p-channel, field effect transistors connected in series between said second and said third n-channel, field effect transistors, each said p-channel, field effect transistor having a gate, a source and a drain terminal, said drain terminal of said first p-channel field effect transistor being connected to said source terminal of said third n-channel field effect transistor, said drain terminal of said second p-channel field effect transistor being connected to said source terminal of said second n-channel field effect transistor, said gate terminal of said first p-channel field effect transistor being connected to the first external terminal and said gate terminal of said second p-channel field effect transistor being connected to the second external terminal; c. a low resistance voltage dropping means connected between said first and said second p-channel field effect transistors; d. a first node located between said second p-channel field effect transistor and said voltage dropping means; e. a second node located between said first p-channel field effect transistor and said voltage dropping means; f. a first means, connected between said second node and said gate terminal of said first p-channel field effect transistor, to maintain a charge on said gate terminal of said first p-channel field effect transistor; and g. a second means, connected between said first node and said gate terminal of said second p-channel field effect transistor, to maintain a charge on said gate terminal of said second p-channel field effect transistor.